PostLab5_248
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Texas A&M University *
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248
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Philosophy
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Apr 3, 2024
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ECEN 248 - Lab Report
Lab Number: 5
Lab Title: Introduction to Logic
Simulation and Verilog
Section Number: 503
Student’s Name: Rushi Penki
Student’s UIN: 532002417
Date: 2/26/24
TA: Yi Deng
Objectives:
Write down what you will learn from this lab and discuss the purpose of the lab. The purpose of this lab is to understand our previous lab's bread-boarding and using actual circuits and turning that into coding. For small designs, circuits were very useful, however as it got more complicated, the usage of circuits became less and less. We will be learning how to develop a simple 4-bit ALU in Verilog using Vivado Design 2015.2. Each module used in the lab will be like previous labs such as using a simple 2-1-MUX, 4-bit MUX, half adder, full adder, and then the full 4-bit ALU. We used Verilog HDL, programming languages are very effective for software development, and truth be told, the same goes for hardware development. Syntax wise, Verilog is similar to the coding language C, and the comments are designed to be similar using the slanted lines (//).
Design:
In the first lab, we had to set up the lab itself so we could code in Vivado. I first logged into Linux and clicked on Applications, and then System Tools so I could find the Terminal. I then I typed "mkdir ecen248" to create a directory for all my files. I then set up the computer to launch Vivado by typing in "source /opt/coe/Xlinix/Vivado/2015.2/settings64.sh". After I finished typing that into the terminal and hitting enter, I then typed in "vivado" to launch the Vivadosuite. After that loaded, I clicked on File, and then New Project to create a new project. I named the project "lab5" and then clicked next to RTL project. When I did that I clicked Next and then until
I got to the Add Sources, and then I made sure both the target language was Verilog and the simulator language was Verilog. I clicked next until the Default Part window was shown, I then
clicked on Boards, and selected "Zybo Z7-10", and then clicked next. I then finished and clicked Finish". After that, within the new project, I clicked on "File" and then "New File”. then added another file named two_bit_mux.v. After that I also created another file called two_bit_mux_tb.v" in the terminal. I had to use the command "VerilogFiles_Fall2021/248NeededFiles/two_one_mux_tb.v." and it created my tb file. As soon as I coded the needed information into the two_bit_mux, I then had to simulate the file using the tb file and that is how I came up with the first image in the results below. In part 2, I created a 4-
bit mux, using the code that was given to us, I created another file, however due to errors in Linux, I had to unfortunately wait another 30 minute wait due to how poorly Vivado ran on the 2015.2 version. However, when the file completed loading, I was able to create the four_bit_mux.v in the files and I created it so that when I finished coding in it and saved it, it would be labeled as a module. I also created another tb file for this file by using the last command however changing it so that it would create the tb file for the four_bit_mux.v. I plugged in this command: "VerilogFiles_Fall2021/248NeededFiles/four_bit_mux_tb.v.". As soon
as I did that I was able to run the simulation and that is how I got my second picture in the results. I rinsed and repeated for the Addition and Subtraction Unit. I coded in the file I created and then I also created a tb file for that so I could fun the simulation and that is how I got the 3
rd
picture in the results. I did the same thing for the last ALU and the 4-bit ALU. I had to get my lab
code and pictures because my Linux and Vivado were wasting my time because it kept freezing.
Results:
The source code is attached to Canvas for easier viewing. I was not able to include comments because of the limited time I had. There were complications with my Linux and Vivado not giving me enough time to complete the assignment even with coming in after lab hours.
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Post Lab Deliverables:
1. module four_bit_mux(Y, A, B, S);
//output is a 4−bit wide wire
input wire [ 3 : 0 ] A, B ; / / A and B are 4− b i t wide wires
input wire S ; // select is till 1 bit wide
/ * instantiate user−defined modules * /
two_one_mux MUX0(Y[ 0 ] , A[ 0 ] , B [ 0 ] , S ) ;
two_one_mux MUX1(Y[ 1 ] , A[ 1 ] , B [ 1 ] , S ) ;
two_one_mux MUX2(Y[ 2 ] , A[ 2 ] , B [ 2 ] , S ) ;
two_one_mux MUX3(Y[ 3 ] , A[ 3 ] , B [ 3 ] , S ) ;
endmodule
`timescale 1ns/1ps
`default_nettype none
module full_adder(S, Cout, A, B, Cin);
/*declare output and input ports*/
//1-bit wires
input wire A, B, Cin;//1-bit wires
output wire Cout, S;
/*decalre internal nets*/
wire andBCin, andACin, andAB;//1-bit wires
/*use dataflow to describe the gate-level activity*/
assign S = A ^ B ^ Cin;//the hate (^) is for XOR
assign andAB = A & B;//the ampersand (&) is for and
assign andBCin = B & Cin;
assign andACin = A & Cin;
assign Cout = andAB | andBCin | andACin;//pipe (|)is for or
endmodule
`timescale 1ns/1ps
`default_nettype none
module add_sub(
/*declare output and input ports*/
output wire [3:0] Sum, //4-bit result
output wire Overflow, //1-bit wire for overflow
input wire [3:0] opA, opB, //4-bit operands
input wire opSel //opSel = 1 for subtract
); // in Verilog, we can describe a module interface in this manner as well!
/*declare internal nets*/
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wire [3:0] notB;
wire c0, c1, c2, c3;
/*create complement logic*/
assign notB[0] = opB[0] ^ opSel;
assign notB[1] = opB[1] ^ opSel;
assign notB[2] = opB[2] ^ opSel;
assign notB[3] = opB[3] ^ opSel;
/*wire up full adders to create a ripple carry adder*/
full_adder adder0(Sum[0], c0, opA[0], notB[0], opSel);
full_adder adder1(Sum[1], c1, opA[1], notB[1], c0);
full_adder adder2(Sum[2], c2, opA[2], notB[2], c1);
full_adder adder3(Sum[3], c3, opA[3], notB[3], c2);
/*overflow detection logic*/
assign Overflow = c3 ^ c2;
endmodule
`timescale 1ns/1ps
`default_nettype none
module four_bit_alu(
output wire [3:0] Result,
output wire Overflow,
input wire [3:0] opA, opB, input wire [1:0] ctrl
);
assign Result=(crtl == 2'b00)? opA + opB:
(crtl == 2'b01)? opA - opB:
(crtl == 2'b00)? opA & opB:
(crtl == 2'b00)? opA | opB:
(crtl == 2'b00)? opA ^ opB:
3'b000;
endmodule
4. Behaviors modeling execute statements sequentially. They are written inside a process statement and the statements are alike with if-else statements, switch cases, and loops. They are part of behavior modeling. There are no looping statements while programing hardware as it's hard to get the loop to integrate or implement on a board.
5. The advantages of bread-boarding are that the concept is similar to functions. We can create the components of each logic gate which is used multiple times in the code. It is also helpful for visual learners who struggle with the concept of coding. The advantage of coding is that it is easier to implement and easier to manage rather some wires. However, it is a hard skill to master rather than just using some wires.
6. I feel like I would do both. There are a lot of different errors in both. In all the equipment are in the software and it is used to make the circuits. It is very useful that we are using Xilinx and other software such as C++ in CSCE 121.
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