Written Assignment 5 PLC Seth Reehs

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Thomas Edison State College *

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CTR-212

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Mechanical Engineering

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Feb 20, 2024

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Chapter 7 2. Draw the symbol and explain the operation of each of the following timed contacts of a mechanical timing relay: a. On-delay timer—NOTC contact Contact is open when relay is de-energized b. On-delay timer—NCTO contact Contact is closed when coil id de-energized c. Off-delay timer—NOTO contact Contact is NO whe coil is de-energized d. Off-delay timer—NCTC contact Contact is NC when coil is de-energized. 3. Name five pieces of information usually associated with a PLC timer instruction 1. Type of timer 2. Timer address 3. Time base of the timer 4. Preset value 5. Accumulated value 4. When is the output of a programmed timer energized? When the preset time equals the accumulated time 5. a. What are the two methods commonly used to represent a timer instruction within a PLC’s ladder logic program? Coil and Block format 6. a. Explain the difference between the operation of a non-retentive timer and that of a retentive timer. A non-retentive timer adds time whenever the device is powered but does not retain the current time when the device loses power. In contrast, a retentive timer accumulates time when the device is powered and retains the current time even if power is removed. b. Explain how the accumulated count of programmed retentive and non-retentive timers is reset to zero.

The reset of a non-retentive timer occurs when there is a loss of logic continuity to the timer rung. On the other hand, a retentive timer is reset by a dedicated reset signal, which could be triggered by an external control element such as a push button or switch. 7. State three advantages of using programmed PLC timers over mechanical timing relays 1. Modifying their settings is a straightforward process. 2. The quantity of timers employed can be adjusted without necessitating any alterations to the wiring. 3. These timers boast high accuracy and repeatability in their timekeeping. 8. For a TON timer: a. When is the enable bit of a timer instruction true? The enable bit becomes true whenever the timer instruction is true. b. When is the timer-timing bit of a timer instruction true? The timer-timing bit is true when the accumulated value of the timer is in the process of changing. c. When does the done bit of a timer change state? The done bit transitions between states when the accumulated value reaches the preset value. 9. For a TOF timer: a. When is the enable bit of a timer instruction true? The enable bit is activated when the timer instruction is true. b. When is the timer-timing bit of a timer instruction true? The timer-timing bit is activated when there is a change in the accumulated value of the timer. c. When does the done bit of a timer change state? The done bit is activated when the timer instruction is true, remaining active until the accumulated value reaches the preset value. 10. Explain what each of the following quantities associated with a PLC timer instruction represents: a. Preset time The duration of the timing circuit. b. Accumulated time The elapsed time since the timing coil was energized. c. Time base The speed at which the timer counts time (e.g., 1s, 5s, 10s, etc.). 11. State the method used to reset the accumulated time of each of the following:

a. TON timer Temporarily force the rung to go false. b. TOF timer Temporarily trigger the rung to go true. c. RTO timer Implement a reset instruction with an identical address to the RTO timer, linking it to the input. 1. a. With reference to the relay schematic diagram in Figure 7-38, state the status of each light (on or off) after each of the following sequential events: I. Power is first applied and switch S1 is open. II. Switch S1 has just closed. III. Switch S1 has been closed for 5 s. IV. Switch S1 has just opened. V. Switch S1 has been opened for 5 s. PL1 PL2 PL3 PL4 On Off On Off On Off Off On Off On Off On On Off Off on On Off On Off b. Design a PLC program and prepare a typical I/O connection diagram and ladder logic program that will execute this hardwired control circuit correctly. 3. Study the ladder logic program in Figure 7-40 and answer the questions that follow: a. What type of timer has been programmed? An on delay timer b. What is the length of the time-delay period? 10 seconds 4. Study the ladder logic program in Figure 7-41 and answer the questions that follow:

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a. What type of timer has been programmed? On-delay timer without retention b. What is the length of the time-delay period? 10 Seconds c. What is the value of the accumulated time when power is first applied? Zero d. When does the timer start timing? When rung 1 transitions from true to false e. When does the timer stop timing and reset itself? When rung 1 transitions from false to true f. When input LS1 is first closed, which rungs are true and which are false? Rungs 1, 3, and 4 are true, while rungs 2 and 5 are false g. When input LS1 is first closed, state the status (on or off) of each output. SOL A off, SOL B on, R on, Y off h. When the timer’s accumulated value equals the preset value, which rungs are true and which are false? Rungs 1, 2, and 4 are true, while rungs 3 and 5 are false i. When the timer’s accumulated value equals the preset value, state the status (on or off) of each output. SOL A off, SOL B off, R on, Y off j. Suppose that rung 1 is true for 5 s and then power is lost. What will the accumulated value of the counter be when power is restored? Zero 6. Study the ladder logic program in Figure 7-43 and answer the questions that follow: a. What is the purpose of interconnecting the two timers? The purpose of the interconnecting timers is to get a longer delay time than that of a single timer. b. How much time must elapse before output PL is energized? The timers in rung 2 and rung 3 are linked. The timer in rung 2 is set to 2900 seconds, while the timer in rung 3 is set to 1780 seconds. Collectively, the two timers have a combined preset value of 4680 seconds.

c. What two conditions must be satisfied for timer T4:2 to start timing? After the completion of the 2900-second count on rung 2 and the transition of the DN status, the closing PB initiates the beginning of T4:2 for timing. d. Assume that output PL is on and power to the system is lost. When power is restored, what will the status of this output be? The RTO instruction retains the timed count, continues counting upon instruction, and persists in counting even when power interruptions occur. Consequently, the output PL remains consistently in the on state as long as the contacts of PB1 are closed. e. When input PB2 is on, what will happen? The reset instruction, RTO, is linked to rung 1. When PB2 is activated, the RTO is triggered, causing both timers to receive a command to reset their accumulated values. f. When input PB1 is on, how much accumulated time must elapse before rung 3 will be true? For rung 3 to become true, the accumulated time must reach 2900. 7. You have a machine that cycles on and off during its operation. You need to keep a record of its total run time for maintenance purposes. Which timer would accomplish this? To maintain a record of a machine's on and off cycles during operation, a retentive on-delay timer would be effective. 8. Write a ladder logic program that will turn on a light, PL, 15 s after switch S1 has been turned on. 9. Study the on-delay timer ladder logic program in Figure 7-44, and from each of the conditions stated, determine whether the timer is reset, timing, or timed out or if the conditions stated are not possible. a. The input is true, and EN is 1, TT is 1, and DN is 0. - The timer's state in the mentioned condition is within the timing condition. b. The input is true, and EN is 1, TT is 1, and DN is 1. The stated conditions are not feasible as DN and TT cannot be in the ON state simultaneously. c. The input is false, and EN is 0, TT is 0, and DN is 0. The described conditions above suggest that the timer is in the reset state, given that EN, TT, and DN are all in the OFF state. d. The input is true, and EN is 1, TT is 0, and DN is 1. These conditions imply that the timer is in the timed-out state. With EN set to 1 and DN also at a state of 1, it indicates that the accumulated time has reached its preset value, marking the completion of the cycle.

10. Study the off-delay timer ladder logic program in Figure 7-45, and from each of the conditions stated, determine whether the timer is reset, timing, or timed out or if the conditions stated are not possible. a. The input is true, and EN is 0, TT is 0, and DN is 1. Given that the input is true, EN should transition to 1. However, in this condition, EN remains at 0. Therefore, the specified conditions are not achievable. b. The input is true, and EN is 1, TT is 1, and DN is 1. If the input is true and EN is 1 while TT is also 1, it is not possible for DN to be in a state of 1. c. The input is true, and EN is 1, TT is 0, and DN is 1. The mentioned conditions above suggest that the timer is in a reset state. d. The input is false, and EN is 0, TT is 1, and DN is 1. - The aforementioned conditions indicate that the timer is in a timing state. e. The input is false, and EN is 0, TT is 0, and DN is 0. The conditions mentioned above indicate that the timer is in a timed-out state. 11. Write a program for an “anti–tie down circuit” that will disallow a punch press solenoid from operating unless both hands are on the two palm start buttons. Both buttons must be pressed at the same time within 0.5 s. The circuit also will not allow the operator to tie down one of the buttons and operate the press with just one button. (Hint: Once either of the buttons is pressed, begin timing 0.5 s. Then, if both buttons are not pressed, prevent the press solenoid from operating.) Chapter 8 1. Name the three forms of PLC counter instructions, and explain the basic operation of each. An Up counter is an output instruction that accumulates its count in increments with a false to true or off to on transition. A Down counter, on the other hand, is an output instruction that accumulates its count in decrements with the occurrence of an event. An Up-Down counter, also known as a combined counter, adjusts its count based on its preset value, increasing or decreasing as needed. 2. State four pieces of information usually associated with a PLC counter instruction. Counter type provides details about the type of counter, whether it's an up-counter, down- counter, or up-down counter. - Counter address holds the counter's address.

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- Counter preset value, specified by an operator, is loaded into the memory location. It can also be viewed as the maximum or reference value for the count. - Accumulated value is the value presented by the counter. 3. In a PLC counter instruction, what rule applies to the addressing of the counter and reset instructions? The addressing rule for the counter and reset instruction stipulates that the counter reset coil should be specified at the same reference address as the counter intended for reset. The reset instruction becomes active whenever the condition in the CTR rung is true. 3. When is the output of a PLC counter energized? The PLC counter output is triggered when a counting event occurs, and this event can be either an Up-count or a Down-count event. 4. When does the PLC counter instruction increment or decrement its current count? The PLC counter instruction will increase or decrease its existing count when a counting event occurs. 5. The counter instructions of PLCs are normally retentive. Explain what this means. The counter is linked to two input conditions for count and reset instructions. The functioning or counting sequence of all PLC counters relies on the leading edge of the input signal. In the case of a retentive counter, the value is preserved even after the processor restarts. 9. Identify the type of counter you would choose for each of the following situations: a. Count the total number of parts made during each shift. Up Counter b. Keep track of the current number of parts in a stage of a process as they enter and exit. Up-Down Counter c. There are 10 parts in a full hopper. As parts leave, keep track of the number of parts remaining in the hopper. Down Counter Chapter 8 Problems 1. a. Counter Up Counter b. Once the cumulative count reaches the predetermined value and C5:1/DN = 1 (50 items counted). c. In the case of C5:1/DN = 0, indicating any time other than when the cumulative value reaches the preset value. d. The value before the power loss (24) remains unchanged.

e. Assuming Rung 4 remained True throughout, the value is 0, as this is the reset instruction. f. Every time Rung 1 transitions from False to True. g. According to this diagram, the count can only be reset when I:1/2 is True, serving as the reset instruction. 2. a. At the start, O/9 is activated since Rung 1 is initially true. However, upon processing Rung 2, O/1 is activated, causing Rung 1 to become false, and O/9 will be deactivated. b. O/9 will stay inactive until the button is pressed once more. 3. a. An up-and-down counter combination. b. Input I:2/6. c. Input I:3/8. d. Input I:4/1. e. Triggered when either the CTU or the CTD reaches 25, resulting in a DN=1 output. f. Increment by 10 in the upward direction. 6.