Lab 4 - ECE 385_ Digital Systems Laboratory (Spring 2022) - Illinois Wiki
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University of Illinois, Urbana Champaign *
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Course
385
Subject
Industrial Engineering
Date
Dec 6, 2023
Type
Pages
4
Uploaded by MatePuppyMaster1948
5/15/23, 11:14 PM
Lab 4 - ECE 385: Digital Systems Laboratory (Spring 2022) - Illinois Wiki
https://wiki.illinois.edu/wiki/display/ECE385SP22/Lab+4
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Created by Julieanne Chapman on Jan 12, 2022
An 8-Bit Multiplier in SystemVerilog
In this experiment, you will design a multiplier for two 8-bit 2’s complement numbers and implement it using SystemVerilog on
the DE10 FPGA board.
Assignment
Read the Lab 4 description in the lab manual and complete the Lab 4 Pre-Lab before the lab section.
Work on Lab 4 report and Lab 5 Pre-Lab after the lab section.
Demo
Reserve your demo slot by enter your name(s)
5/15/23, 11:14 PM
Lab 4 - ECE 385: Digital Systems Laboratory (Spring 2022) - Illinois Wiki
https://wiki.illinois.edu/wiki/display/ECE385SP22/Lab+4
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Current Demo:
Final Demo (in-person) 5/5
Find your section below and sign up for a demo/quiz slot
by entering you and your partner's NetIDs
Note: do not sign up prior to the Wednesday (8:00 PM CST) before the demo, as
available demo slots will not be finalized until then. If you do, you will be deleted
when the demo schedule updates.
Zoom room for demos are found on your TA's page
Remember to zip and upload your code to Canvas (only one upload per group)
Landing Page
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Functional simulation completes successfully. It should include multiplications using different signs (e.g., 7*59, -7*59,
7*-59, -7*-59) (1 point).
Reset_Load_Clear
works on the board. (1 point)
Multiplication works. We will test * , * , * , and * . (1 points)
Consecutive multiplications work, like -1 * -1 * -1 * ... . Reset_Load_Clear will not be pressed between two presses
of Run.
(1 points) (
UPDATED: 09/17/20
)
Note - this is only expected to work if the product from the previous multiplication operation can be truncated to
fit into 8-bits without changing the value (e.g. the product is within the range [-128,127])
-1 (16'b1111111111111111) is truncated to (8'b11111111), which is still interpreted as -1, so this is expected to
work for consecutive multiplications.
256 (16'b0000000100000000) is truncated to be 8'b00000000, which is not interpreted as 256, so this is not
expected to work for consecutive multiplications.
Execution cycle responds correctly – exactly one execution per press of the “Run” button. (1 point)
5/15/23, 11:14 PM
Lab 4 - ECE 385: Digital Systems Laboratory (Spring 2022) - Illinois Wiki
https://wiki.illinois.edu/wiki/display/ECE385SP22/Lab+4
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Updates
FAQ
"How do we copy over Pin assignments from our last lab?"
The .qsf file in you project stores the pin assignments.
"Can you elaborate on number 4 of the required demo listed above?"
It just means that your circuit should run the multiplication several times without resetting the circuit (for
example, we'll do 2x2=4 first, then 4x2=8, then 8x2=16 and so on by only pressing the 'Run' button several
times without pressing the Reset_Load_Clear
in between). Note that you will not need to guarantee correct
operation if the result XAB doesn't fit into 8-bits,
but negative numbers should still work for consecutive
multiplies
.
"What's the point of "reset?" In our state machine it cycles back to the initial/start state after completing the
full operation, so I don't see why it's useful."
You're right that 'Run' and 'ClearA_LoadB' are pretty much all that you need. But it's good to have a reset
capability for any circuit. That's why your computer has the 'restart' option on top of the 'shut down', right?
"Suppose we hold down the run button through an entire cycle; it should wait for the run button to go low
before starting another multiplication cycle, correct?"
Yes your circuit should wait for the run to go low before another calculation is performed, i.e., one multiplication
per run.
"My state machine does an add in one state, then a shift in the next state, then another add, and so on until the
multiplication is done. All these states proceed to the next state regardless of any input values i.e.
when A
next_state = B
for all the adds and shifts. Does the symbolic state machine in the SV code ensure that exactly one shift will
occur in each state, no more and no less, or exactly one add and load operation? Or do we need a signal that
says when it's OK to move to the next state."
Each state will only be executed for the duration of a single clock cycle, which will only shift your register
precisely once if you have raised the shift control signal during that state. You don't need separate signal to
monitor the shift.
"My state machine is designed to skip ADD states when M=0, but it sometimes goes to those ADD states when
M is clearly 0. What do I do?"
Since the actual shift occurs at the end of a SHIFT state, M does not get updated until after the state machine
transitions to the next state. To fix this, just define M as B[1] instead of B[0], since B[1] would be M after the shift.
"My compilation time is very long on the EWS machines"
Make sure you are not trying to compile across the network. Copy the work directory to a temporary folder in
the C:\ECE385temp folder
, and remember to move it back to your home network drive and delete your
temporary copy after you are done. "Quartus returns an error when trying to start RTL simulation about the ModelSim directory not being found"
Set the ModelSim directory under Quartus - go to Tools→Options then set the following directory:
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5/15/23, 11:14 PM
Lab 4 - ECE 385: Digital Systems Laboratory (Spring 2022) - Illinois Wiki
https://wiki.illinois.edu/wiki/display/ECE385SP22/Lab+4
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