HW5
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Subject
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Date
Feb 20, 2024
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Sahil Shah EE271-HW5
013731847
Q1. In the case of an edge triggered sequential element, the Setup Time is the time interval before the
active clock edge during which the data should remain unchanged. In other words, each flip-flop (or any sequential element, in general) needs some time for the data to remain stable before the clock edge arrives, such that it can reliably capture the data. This duration is known as setup time.
For the same case, the Hold Time is the time interval after the active clock edge during which the
data should remain unchanged. Similar to setup time, each sequential element needs some time for data to remain stable after the clock edge arrives to reliably capture data. This duration is known as hold time. The image below shows the Setup Time and Hold Time for an edge triggered Flip-Flop Register.
Sahil Shah EE271-HW5
013731847
Q2. Slack is the difference between the data required time and the data arrival time. There are two forms of slack, positive and negative slack. Negative slack indicates that constraints have not been met, while positive slack indicates that constraints have been met. Q3. Between the setup and hold time violation on the chip, the hold time violation is worse because it
means that the output will not be correct and there is an issue with the design. It is possible to increase the period of the clock by decreasing the frequency but hold time might have a problem with design. Q4.
A multicycle path is a path where there are multiple clock cycles used so that the data can make it to the capturing flip flop from the launching flip flop. To check the setup and hold violations we can use primetime to do the calculations. Primetime will provide the timing analysis and will calculate if there is a violation since it will be negative.
Sahil Shah EE271-HW5
013731847
Q5. a.
F
clk
= 100MHz, T
clk
= 1/F
clk
= 10nS
T
clk
> t
C2Qmax
+ t
CLmax
+ t
su
+ |t
skew
| t
CLmax
= 3nS + 4nS =7nS
t
C2Qmax
= 3ns t
skew
= 1ns (positive skew)
Therefore, t
clk
> t
C2Qmax
+ t
CLmax
+ t
sumax
- t
skew
= 7ns+3ns-1ns = 9ns 10ns > 9ns (Setup time constraint is met)
b.
t
C2Qmin
+ t
CLmin
> t
h
+ t
skew
t
h
= 3.5 t
skew
= 1ns t
C2Qmin
= 1ns t
CLmin
= 2ns Does not meet hold time constraint
If the device does not meet the hold time constraint, you can make design changes to the combinational block so that the time delay is longer. Also if there is a larger amount of slack in the set up time then the delay can be increased so that the hold time can also be met while still maintaining the set up time condition.
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Sahil Shah EE271-HW5
013731847
Q6. a) MAC unit design with all kernels shown below
`timescale
1ns /
1ps
module conv
(
input i_clk,
input [
71
:
0
] i_pixel_data,
input i_pixel_data_valid,
output reg [
7
:
0
] o_convolved_data,
output reg o_convolved_data_valid
);
integer i;
reg [
7
:
0
] kernel1 [
8
:
0
];
reg [
7
:
0
] kernel2 [
8
:
0
];
reg [
7
:
0
] kernel3 [
8
:
0
];
reg [
7
:
0
] kernel4 [
8
:
0
];
reg [
7
:
0
] kernel5 [
8
:
0
];
reg [
10
:
0
] multData1[
8
:
0
];
reg [
10
:
0
] multData2[
8
:
0
];
reg [
10
:
0
] multData3[
8
:
0
];
reg [
10
:
0
] multData4[
8
:
0
];
reg [
10
:
0
] multData5[
8
:
0
]; reg [
10
:
0
] sumDataInt1;
reg [
10
:
0
] sumDataInt2;
reg [
10
:
0
] sumDataInt3;
reg [
10
:
0
] sumDataInt4;
reg [
10
:
0
] sumDataInt5;
reg [
10
:
0
] sumData1;
reg [
10
:
0
] sumData2;
reg [
10
:
0
] sumData3;
reg [
10
:
0
] sumData4;
reg [
10
:
0
] sumData5;
reg multDataValid;
reg sumDataValid;
reg convolved_data_valid;
reg [
20
:
0
] convolved_data_int1;
reg [
20
:
0
] convolved_data_int2;
reg [
20
:
0
] convolved_data_int3;
Sahil Shah EE271-HW5
013731847
reg [
20
:
0
] convolved_data_int4;
reg [
20
:
0
] convolved_data_int5;
wire [
21
:
0
] convolved_data_int;
reg convolved_data_int_valid;
initial
begin
kernel1[
0
] = 0
; //identity
kernel1[
1
] = 0
;
kernel1[
2
] = 0
;
kernel1[
3
] = 0
;
kernel1[
4
] = 1
;
kernel1[
5
] = 0
;
kernel1[
6
] = 0
;
kernel1[
7
] = 0
;
kernel1[
8
] = 0
;
kernel2[
0
] = 0
; //Ridge
kernel2[
1
] = -
1
;
kernel2[
2
] = 0
;
kernel2[
3
] = -
1
;
kernel2[
4
] = 4
;
kernel2[
5
] = -
1
;
kernel2[
6
] = 0
;
kernel2[
7
] = -
1
;
kernel2[
8
] = 0
;
kernel3[
0
] = 0
.
111
; //box-blur
kernel3[
1
] = 0
.
111
;
kernel3[
2
] = 0
.
111
;
kernel3[
3
] = 0
.
111
;
kernel3[
4
] = 0
.
111
;
kernel3[
5
] = 0
.
111
;
kernel3[
6
] = 0
.
111
;
kernel3[
7
] = 0
.
111
;
kernel3[
8
] = 0
.
111
;
kernel4[
0
] = 0
; //Sharpen
kernel4[
1
] = -
1
;
kernel4[
2
] = 0
;
Sahil Shah EE271-HW5
013731847
kernel4[
3
] = -
1
;
kernel4[
4
] = 5
;
kernel4[
5
] = -
1
;
kernel4[
6
] = 0
;
kernel4[
7
] = -
1
;
kernel4[
8
] = 0
;
kernel5[
0
] = 0
.
0625
; //Gaussian Blur
kernel5[
1
] = 0
.
125
;
kernel5[
2
] = 0
.
0625
;
kernel5[
3
] = 0
.
125
;
kernel5[
4
] = 0
.
25
;
kernel5[
5
] = 0
.
125
;
kernel5[
6
] = 0
.
0625
;
kernel5[
7
] = 0
.
125
;
kernel5[
8
] = 0
.
0625
;
end always @(
posedge i_clk)
begin
for (i = 0
; i < 9
; i = i + 1
)
begin
multData1[i] <= $
signed
(kernel1[i]) * $
signed
({
1'b0
, i_pixel_data[i
*
8
+
:
8
]});
multData2[i] <= $
signed
(kernel2[i]) * $
signed
({
1'b0
, i_pixel_data[i
*
8
+
:
8
]});
multData3[i] <= $
signed
(kernel3[i]) * $
signed
({
1'b0
, i_pixel_data[i
*
8
+
:
8
]});
multData4[i] <= $
signed
(kernel4[i]) * $
signed
({
1'b0
, i_pixel_data[i
*
8
+
:
8
]});
multData5[i] <= $
signed
(kernel5[i]) * $
signed
({
1'b0
, i_pixel_data[i
*
8
+
:
8
]});
end
multDataValid <= i_pixel_data_valid;
end
always @(
*
)
begin
sumDataInt1 = 0
;
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013731847
sumDataInt2 = 0
;
sumDataInt3 = 0
;
sumDataInt4 = 0
;
sumDataInt5 = 0
;
for (i = 0
; i < 9
; i = i + 1
)
begin
sumDataInt1 = $
signed
(sumDataInt1) + $
signed
(multData1[i]);
sumDataInt2 = $
signed
(sumDataInt2) + $
signed
(multData2[i]);
sumDataInt3 = $
signed
(sumDataInt3) + $
signed
(multData3[i]);
sumDataInt4 = $
signed
(sumDataInt4) + $
signed
(multData4[i]);
sumDataInt5 = $
signed
(sumDataInt5) + $
signed
(multData5[i]);
end
end
always @(
posedge i_clk)
begin
sumData1 <= sumDataInt1;
sumData2 <= sumDataInt2;
sumData3 <= sumDataInt3;
sumData4 <= sumDataInt4;
sumData5 <= sumDataInt5;
sumDataValid <= multDataValid;
end
always @(
posedge i_clk)
begin
convolved_data_int1 <= $
signed
(sumData1) * $
signed
(sumData1);
convolved_data_int2 <= $
signed
(sumData2) * $
signed
(sumData2);
convolved_data_int3 <= $
signed
(sumData3) * $
signed
(sumData3);
convolved_data_int4 <= $
signed
(sumData4) * $
signed
(sumData4);
convolved_data_int5 <= $
signed
(sumData5) * $
signed
(sumData5);
convolved_data_int_valid <= sumDataValid;
end
assign convolved_data_int = convolved_data_int1 + convolved_data_int2 + convolved_data_int3 + convolved_data_int4 + convolved_data_int5;
always @(
posedge i_clk)
begin
if (convolved_data_int > 4000
)
Sahil Shah EE271-HW5
013731847
o_convolved_data <= 8'hff
;
else
o_convolved_data <= 8'h00
;
o_convolved_data_valid <= convolved_data_int_valid;
end
endmodule
b) testbench for integrated IP
`timescale
1ns /
1ps
`define headerSize 1080
`define imageSize 512
*
512
module tb
();
reg clk;
reg reset;
reg [
7
:
0
] imgData;
integer file,file1,i;
reg imgDataValid;
integer sentSize;
wire intr;
wire [
7
:
0
] outData;
wire outDataValid;
integer receivedData
=
0
;
initial
begin
clk = 1'b0
;
forever
begin
#5 clk = ~
clk;
end
end
initial
begin
reset = 0
;
sentSize = 0
;
Sahil Shah EE271-HW5
013731847
imgDataValid = 0
;
#100
;
reset = 1
;
#100
;
file = $fopen
(
"lena_gray.bmp"
,
"rb"
);
file1 = $fopen
(
"blurred_lena.bmp"
,
"wb"
);
for
(i
=
0
;i
<
`headerSize
;i
=
i
+
1
)
begin
$fscanf(file,
"%c"
,imgData);
$fwrite(file1,
"%c"
,imgData);
end
for
(i
=
0
;i
<
4
*
512
;i
=
i
+
1
)
begin
@(
posedge clk);
$fscanf(file,
"%c"
,imgData);
imgDataValid <= 1'b1
;
end
sentSize = 4
*
512
;
@(
posedge clk);
imgDataValid <= 1'b0
;
while
(sentSize < `imageSize
)
begin
@(
posedge intr);
for
(i
=
0
;i
<
512
;i
=
i
+
1
)
begin
@(
posedge clk);
$fscanf(file,
"%c"
,imgData);
imgDataValid <= 1'b1
; end
@(
posedge clk);
imgDataValid <= 1'b0
;
sentSize = sentSize
+
512
;
end
@(
posedge clk);
imgDataValid <= 1'b0
;
@(
posedge intr);
for
(i
=
0
;i
<
512
;i
=
i
+
1
)
begin
@(
posedge clk);
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Sahil Shah EE271-HW5
013731847
imgData <= 0
;
imgDataValid <= 1'b1
; end
@(
posedge clk);
imgDataValid <= 1'b0
;
@(
posedge intr);
for
(i
=
0
;i
<
512
;i
=
i
+
1
)
begin
@(
posedge clk);
imgData <= 0
;
imgDataValid <= 1'b1
; end
@(
posedge clk);
imgDataValid <= 1'b0
;
$fclose
(file);
end
always @(
posedge clk)
begin
if
(outDataValid)
begin
$fwrite(file1,
"%c"
,outData);
receivedData = receivedData
+
1
;
end
if
(receivedData == `imageSize
)
begin
$fclose
(file1);
$stop
;
end
end
imageProcessTop dut
(
.axi_clk(clk),
.axi_reset_n(reset),
.i_data_valid(imgDataValid),
.i_data(imgData),
.o_data_ready(),
.o_data_valid(outDataValid),
.o_data(outData),
.i_data_ready(
1'b1
),
Sahil Shah EE271-HW5
013731847
//interrupt
.o_intr(intr)
)
; endmodule