Lab3

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School

Concordia University *

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Course

212

Subject

Electrical Engineering

Date

Jan 9, 2024

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docx

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Experiment #3 COEN 212 - E Lab Section DX For Mr. Ted Obuchowicz Prince Raphael Johnson, #40153375 Date Performed: November 6 th , 2023 Date Due: November 20 th , 2023 I certify that this submission is my original work and meets the faculty’s demands of originality.” Prince Raphael Johnson, November 6 th , 2023

Objectives The main objective of this 3 rd experiment is for students to be gain experience with multiplexer and word-sized operands, as well as designing adder circuit. Introduction In this lab #3, we get to build a 2-1 multiplexer (also called a MUX), which is a component that selects one of many inputs to a single output, and a multiplexer with m number of select lines will have up to 2 m number of inputs (e.g., 2 select lines will result in 4 inputs). We will have various truth table at our discretion to build the different adder circuit mentioned in the lab manual (full adder and half adder). Results Table 1: Truth table for 2-to-1 MUX Table 2: Truth table for word-sized MUX A B C arry S 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 Table 3: Truth table for Half Adder A B C in C arry S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 S IN0 IN1 OUT 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 S IN0 IN1 OUT_0 OUT_1 0 1 1 0 0 IN0_0 IN0_1 0 1 1 1 1 IN1_0 IN1_1

0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Table 4: Truth table for Full Adder During the experiment, the 2-to-1 MUX was built first as it was fairly easy to put together, followed by Word-Sized version, for which the schematic had to be redrawn in order to get the proper input and output, and then, finishing off with the Half and Full Adder which were both pretty straightforward. Questions 1) How many rows would the truth table of a combinational 32-bit parallel adder contain? Express your answer as a power of two. State any assumptions you may have made in order to deduce your answer? - For a 3-bit adder we have 3 input (A, B and C in ) so 2 3 rows or 8 rows. For a 32-bit parallel adder, there will be 32 full adders each with 3 input, so 3*32= 96 inputs. So, we could then assume that its truth table would have 2 96 rows. 2) Would it be practical to design a 32-bit parallel adder using the techniques of Boolean minimization to obtain the SOP expressions for each of the outputs - No, it would not be so, considering that truth table would be too big and minimization for such expression would have too many variables 3) How many full-adders would be required to construct a 32-bit ripple carry adder? - A 2-bit carry adder required 2 full adder. For n -bit ripple carry adder, we would have n full adders, so a 32-bit ripple carry adder would then need 32 full adders. Conclusions With the goal being to design and implement adders and multiplexers, this lab was successful and didn’t take too long to complete. The results obtained during the lab were in accordance with the one obtained in the pre-lab and demonstrated our ability to built and implement the given circuit.

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