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Name _______________ ECE 422 H/W-7 (30 points) Due: Monday, Dec. 4 before class (Performance Calculation) 1. Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI (class A, B, C, and D). A processor P1 with a clock rate of 2.5 GHz and CPIs of 1,2,3, and 3, and a processor P2 with a clock rate of 3 GHz and CPIs of 2,2,2, and 2. Given a program with 10^6 instructions divided into classes as follows: 10% class A, 20% class B, 50% class C, and 20% class D. ( Show your equations for partial points.) 1.1. (5 points) What is the global CPI for each implementation? 1.2. (5 points) Which processor is faster: P1 or P2? And how much faster?

(Pipeline Operation) 2. Suppose we have the following latencies for major functional units: IF ID EX MEM WB 250 ps 350 ps 150 ps 300 ps 200 ps Assume that instructions in a program are grouped in percentage as follows: ALU beq lw sw 40% 20% 20% 20% 2.1(2 points) What is the clock cycle time in a pipelined and non-pipelined processor? 2.2(3 points) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?

2.3(5 points) Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes before another is fetched. In this organization, an instruction only goes through stages it actually needs. For example, ALU only takes 4 cycles because it does not need the MEM stage. Compare clock cycle times and execution times with single-cycle, multi- cycle, and pipelined organization.

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(Pipeline Hazard) 3. We have the following code to run: add $s0, $t0, $t1 sub $t2, $s0, $t3 lw $t4, 0($t5) Suppose we run the MIPS assembly code in the following 5-stage pipelined datapath: 3.1. (3 points) What kind of pipeline hazard are we going to have if we run the code in pipelining?

(7 points) Let’s design a logic circuit in the “Hazard detection unit” to insert a bubble, i.e., NOP. Inserting a NOP is generating 0 for all control signals, and disabling PC and pipeline registers. In this design, you need to design a logic circuit controlling NOP_EN signal by using the following input signals. Basically, provide the condition for the output signal NOP_EN. Input signals - IF/ID.Rs: operand for 1 st source register (5 bits) in IF/ID stage - IF/ID.Rt: operand for 2 nd source register (5 bits) in IF/ID stage - ID/EX.Rt: operand for 2 nd source register (5 bits) in ID/EX stage Output signal - NOP_EN = 0, normal operation - NOP_EN = 1, inserting a bubble, i.e., NOP

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