ECE310_-_2015_Final_Exam

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ECE 310 sec. 001 North Carolina State University Dec 8, 2015 Final Exam D Dept. of Electrical and Computer Engineering Page 1 of 4 Final Exam Name: • 8 problems, 4 pages • Scoring for each problem is given in points beside the problem. • You have 3 hours to complete the test. Problem 1) (20 points) Statement True/False Comment Default value of Wire is X false Z Default value of Register is Z false X 8’hF5 is an 8 bit value True/False? true xor x(A,B,O); O is the output of this xor gate. false A is the output reg [7:0] MEM [0:15]; defines a memory that is 15 bytes false 16 bytes To exhaustively test an 8 input module we would need 128 vectors. False 2exp8 = 256 assign O = sel ? B : A; O can be defined as a register. false O has to be a wire a = 4'b0010; a = a >> 1; and a = a >>> 1 are the same. True Since Msb is 0 if A = 4’b1010; then {4{A[1]},4{A[3]}} = 0xAA false 0xFF or #5 a(x,y,z); Is same as assign #5 x = y|z; True Problem 2) (5 points) Based on the schematic to the right, list the following: Number of Ports? 5 Number of Internal Nets? (do not include ports) 3 Number of Symbols? 3 ( xor , and, or ) Number of Instances? 5 ( 2 xor, 2 and & 1 or ) This study source was downloaded by 100000835970635 from CourseHero.com on 11-22-2022 17:55:11 GMT -06:00 https://www.coursehero.com/file/35418821/final-15-solpdf/

ECE 310 sec. 001 North Carolina State University Dec 8, 2015 Final Exam D Dept. of Electrical and Computer Engineering Page 2 of 4 Problem 3) ( 5 points) Which of the following Signals A, B, Cin, S, Cout, w1, w2 and w3 can be defined as registers. Why? Since it is a gate level modelling all of them are instances of modules. Hence none of them can be registers. All of them have to be wires. Problem 4) (10 points) Draw the circu it modelled by the following code? module problem3(); input clk,reset,enable,A,B,qin; output reg data; always @ (posedge clk) if (reset) begin data <= 0; end else if (enable) begin data <= q_in; end always @ (A, B) begin qin = A^B; end endmodule Diagram Problem 5) (5 points) Assume that a direct-mapped cache has been designed with the following characteristics: • 64-bit address • 32-bit words • 16 words per block/line • 64 blocks/lines in cache This study source was downloaded by 100000835970635 from CourseHero.com on 11-22-2022 17:55:11 GMT -06:00 https://www.coursehero.com/file/35418821/final-15-solpdf/

ECE 310 sec. 001 North Carolina State University Dec 8, 2015 Final Exam D Dept. of Electrical and Computer Engineering Page 3 of 4 (a) How many offset bits are in the address? 16 word per line = 4 offset bits. (b) How many index bits are in the address? 64 lines in cache 6 bits (c) How many tag bits are in the address? 64 bit address. Hence 64 – 6 – 4 = 54 tag bits. Problem 6) ( 15 points ) Write Verilog code for following circuit in gatelevel, dataflow and behavioral flows. //Gatelevel using primitive //verilog gates module AA (A, B, C,Y); input A, B, C; output Y; and(ab,a,b); not(cbar,c); not(ccbar,cbar); not(abbar,ab); and(y,abbar,ccbar); endmodule //Dataflow using assign //statements. module AA (A, B, C,Y); input A, B, C; output Y; assign y = ( (~ (a & b))|(~(~c)); endmodule //Behavioural using always module AA (A, B, C,Y); input A, B, C; output Y; reg y; always @ (*) y = ( (~ (a & b))|(~(~c)); endmodule Problem 7) (20 points) Draw and write code for a simple pattern detector. The circuit has a one bit input A and one bit output B. It has to detect pattern 001 and 100. The circuit has a clock input Clk and Reset input Rst. Rst is asserted first to bring the internal state to all zero. We then serially append the input A to the LSB and check if the pattern is detected. If detected we have to set output B to high. FSM This study source was downloaded by 100000835970635 from CourseHero.com on 11-22-2022 17:55:11 GMT -06:00 https://www.coursehero.com/file/35418821/final-15-solpdf/

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ECE 310 sec. 001 North Carolina State University Dec 8, 2015 Final Exam D Dept. of Electrical and Computer Engineering Page 4 of 4 Verilog code. Problem 8) (20 points) Write a test bench for problem 7. Use Rand function to randomize input A N ame: Student ID: I certify that I did not copy the answers to this exam and did not let anyone copy my answers (sign): __________________________________________________ This study source was downloaded by 100000835970635 from CourseHero.com on 11-22-2022 17:55:11 GMT -06:00 https://www.coursehero.com/file/35418821/final-15-solpdf/ Powered by TCPDF (www.tcpdf.org)