virtual lab 6_ELD-302-aug21

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Thomas Edison State College *

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302

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Electrical Engineering

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Apr 3, 2024

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ELD-302: DIGITAL ELECTRONICS Virtual Lab 6—Counters and Logic Analyzer Complete all the experiments given below and write the lab report using the format provided in the module details. EXPERIMENT 1 Of the three types of multivibrators, bistable and monostable were studied in the previous lab. This experiment introduces the astable multivibrator, which is a free running clock. The 555 timer IC will be used once again. The use of the 555 timer is an astable multivibrator shown in Fig 7-56 of the textbook. Equation 7-4 gives the formula for determining the frequency for given values of R and C components. Additionally, Fig 7-58 provides pre-calculated values of frequencies from 0.1 Hz to 100 kHz for given values of R and C components. Use Equation 7-4 to design astable multivibrators with the following specifications: a) Frequency = 10 kHz; Duty cycle = 60% b) Frequency = 1 MHz; Duty cycle = 75% Show your working for the values of C1, R1, and R2 for both cases. Now, implement these circuits in Multisim, connecting the output to an oscilloscope in each case. Provide screenshots for both circuits, with the oscilloscope clearly showing the frequency and duty cycle. If you look at Equations 7-5 and 7-6, which give the “high” time and “low” of the astable multivibrator, you will see that it is not possible to set a duty cycle of less than 50% using this circuit. The textbook shows a way to have duty cycles of less than 50% using a diode. However, another way of doing it is to use the astable output to trigger a monostable in every cycle, as was done in Experiment 3-B in Virtual Lab 5. Use this approach to create a 100 Hz square wave with a 10% duty cycle. Implement this circuit in Multisim and provide a screenshot of the simulation with the oscilloscope clearly displaying the final waveform. Copyright © 2021 by Thomas Edison State University. All rights reserved.

EXPERIMENT 2 In this experiment, you will build up on Experiment 4 of Virtual Lab 4, and automate the display of numbers on the 7-segment display. You will have observed that the final output in the previous experiment looked less like a clock and more like that of a pulse generator. When the duty cycle is very low, just a few percent, the output resembles a positive going pulse train. When the duty cycle is increased to just a few percent below 100, it will resemble a negative going pulse train. Now it is impossible to use an astable and a monostable to create a pulse train and use it to replace the push button input for stepping through the numbers and automatically changing the numbers being displayed on the 7-segment display. This should be fairly straightforward to set up. Start with a frequency of about 1 Hz for changing the numbers being displayed, then increase or decrease the frequency to set up a comfortable display where the numbers can be easily distinguished. Provide the final pulse frequency that you used, along with calculations for the values of the components used. Also provide a screenshot of the simulation circuit with the oscilloscope clearly showing the pulse train. EXPERIMENT 3 The purpose of this experiment is to introduce a new powerful tool, the Multisim Logic Analyzer. It is able to accept 16 input channels and you can display all the channels to study the relative timing diagram of these signals. A logic analyzer is an important tool in a digital design and troubleshooting laboratory. To learn the use of the Logic Analyzer, you will repeat Example 3-6 of the textbook, adding the Logic Analyzer to it. Recall that you did this example earlier in Virtual Lab 2, as Experiment 5. Here is the modified circuit: Copyright © 2021 by Thomas Edison State University. All rights reserved.

We have retained the 4-channel scope so that you may see that the circuit is working while trying to set up the Logic Analyzer. The next picture shows the setup of the Word Generator: This should give you the oscilloscope display, as before: Copyright © 2021 by Thomas Edison State University. All rights reserved.

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The next picture shows you how to set up the clock on the Logic Analyzer: Finally, run the simulation and this is what you should see: Copyright © 2021 by Thomas Edison State University. All rights reserved.

You can see any part of the recorded trace by doing a horizontal scroll. It is possible to make time measurements by placing the two vertical cursors to the desired positions. To complete the experiment, measure and report the periods of the signals on channels 1, 2, and 3, as well as the width of the positive going pulse on channel 4. Finally, attach a screenshot of the Logic Analyzer window with cursors set for any one of the above measurements. EXPERIMENT 4 The purpose of this experiment is to learn to use Divide by N, or Modulo N counters to divide the frequency of a square wave by a number N. Our aim is to develop a divide by 60 circuit, which is very useful in clock-related applications because it can be used to convert seconds into minutes and minutes into hours. Although it is possible to come up with a single divide by 60 counter, it is a little more complicated. It is easier, and more instructive, to use divide by 5 and divide by 12 counters, which may be cascaded to achieve divide by 60. Make a Modulo 5 counter first. You may use a 74LS90 BCD counter chip. The reset condition would be Q0 and Q2 being high. Next use a 4-bit synchronous counter to make a Modulo 12 counter. The reset condition would be Q3 and Q4 being high. Copyright © 2021 by Thomas Edison State University. All rights reserved.

Place a Digital Clock and set the frequency to 60 kHz. Connect the 60 kHz signal to the clock input of the cascaded counters. The output should be 1 kHz. Use oscilloscopes to display the input and output frequencies. Provide a screenshot of the circuit with the oscilloscopes clearly displaying the time periods through the cursors placed for one cycle time. EXPERIMENT 5 The purpose of this experiment is to verify the design of an irregular binary counter presented in the textbook as Example 9-4. The final project will require designing a similar counter. This exercise will result in developing a better understanding of the concepts involved. Example 9-4 can be found on pages 509-511 of the electronic version of the textbook. The state diagram of the counter is presented in Figure 9-30 and Table 9-10. The final implementation of the counter is shown in Figure 9-32. Start by implementing the given design in Multisim. It has one clock input for stepping through the states and three bits of output identifying the states. You will need to connect a push button driven pulse output to the input so you may step through the states to verify the design. You will also need to connect digital probes or LEDs to the three outputs, Q0, Q1, and Q2. The experiment will involve stepping through the states by sending pulses to the counter. Report your findings. Also attach a screenshot of the circuit, with the counter being in a valid state. Copyright © 2021 by Thomas Edison State University. All rights reserved.

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