Lab3_manual_UG_GR

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ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 1 1 Introduction In this lab, we will extend our IIR design done in the previous lab. We will implement unfolded and folded IIR filter designs and compare their differences. For this lab, you are expected to complete the following tasks: a) Implement the unfolded IIR filter design. b) Implement the folded IIR filter design. c) Summarize the differences in the implementation between unfolding and folding filter design. 1.1 Introduction to Unfolding and Folding Unfolding is a transformation technique that increases the throughput of a digital signal processing program by duplicating the functional blocks while maintaining functionality. On the other hand, folding converts multiple operations into a single operation block and minimizes the number of functional blocks needed in synthesizing the digital signal processing system. Please refer to the lectures (or chapters 5 and 6 from the text authored by Keshab Parhi prescribed in the syllabus) to understand the unfolding and folding algorithms before the lab. We need to design IIR for this lab based on the same IIR design. Figure 1, Figure 2, and Figure 3 show the original, unfolded, and folded design of the IIR filter, respectively. Figure 1: IIR Original Design

ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 2 Figure 2: IIR Unfolded Design Figure 3: IIR Folded Design 2 Lab Design of Unfolded IIR Now we start to implement the designs. a) If using Olympus server, transfer the base_vivado.zip file form personal computer to Olympus using the scp command (instructions shown in Lab1). b) Log into Olympus. Unzip the zip file. Rename the extracted directory from base_vivado to lab3_vivado c) Source the 2023 version of Vivado and Vitis: source /opt/coe/Xilinx/Vitis/2023.1/settings64.sh source /opt/coe/Xilinx/Vivado/2023.1/settings64.sh d) Start Vivado, then open the project base.xpr under lab3_vivado/base

ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 3 e) Click on File à Add Sources . Select Add or create design sources . Click Add Files and choose the files IIR_unfold.v , multiply.v from the lab3_codes folder. Finally and click finish . Refer to figure. f) In the same manner, also add the testbench for the design. Click on File à Add Sources . Select Add or create simulation sources . Choose the file IIR_unfold_tb.v and flick Finish. Refer to the figure below on how the design hierarchy should look after adding these files. g) Now its your job to complete the Verilog code for the 2-unfolded IIR module according to the unfolding algorithm taught in class. You will need to implement your code in the IIR_unfold.v file. Remember to use an 8-bit signed fixed-point number for calculation in the lab, with 4 bits for the fractional part, 3 bits for the interger part and 1 bit for sign. After you finish coding IIR_unfold.v , we can run behavioral simulation. Before simulation, please right click on IIR_unfold_tb and click Set as Top . Refer to figure below.

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ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 4 h) Start simulation but clicking run simulation à run behavioral simulation in the flow navigator pane on the left. Now you shoulw see the waveform of the simulation. Change the radix to fixed point, signed and binary point value to 4. If your design and testbench are correct, you should be able to see the filtered waveform on the output ports of your IIR design. 3 Implementation of Unfolded IIR on FPGA Next, we need to implement the design on FPGA. a) Add top_IIR_unfold.v into your project. Once added, right click this file in the “ source ” panel and click “ set as top ”. The file should appear in blod after this step. Refer to figure below b) Now, we need to add a dual port RAM IP that is instantiated in the top_IIR_unfold.v . This ram will be instantiated in the FPGA and will be used to store the input/output values for the IIR fitler. c) Double click on “blk_mem_gen_0” to customized the “block memory generator”. If a window pops up, choose customize IP.

ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 5 d) Select True Dual Port Ram since we need a two port ram. e) In both port A and port B options, change write width to 16, and write depth to 65536. f) Choose operation mode Read First , enable port type Always Enabled . Click “ok” . g) In the pop-up window, select “ Global ” in the synthesis option, and click “generate” . h) Now, click generate bitstream . After the bitstream is generated, open the implemente design and make sure the Total Negative Slack is zero as shown below. This ensures the design will work properly on the FGPA for the given clock frequency.

ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 6 i) Now click file->export->export hardware . Click Next . Check Include bitstream . Click Next two times in the following screens and and finally click Finish . Refer to figure below.

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ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 7 Now, we use can implement the design on the Zybo board. a) Refer to HowToImplementDesignOnFPGA.pdf for the details. b) Once you boot the Linux system on the Zybo board, run the testing program with the command: ./lab3_IIR_unfold_test c) The results are written into lab3_IIR_unfold_results . (Check it by ls command) d) Please screenshot the output in the terminal, and attach it in the post-lab report. e) In your computer, plot the data in lab3_IIR_unfold_results using your favorate tool, and attach it in the post-lab report. 4 Design and Implement Folded IIR (For Graduate Students) a) Repeat Section 2 and 3 to design a 4-folded IIR, with files: IIR_fold.v , IIR_fold_tb.v . Run the behavior simulation of the folded IIR design, and include it in the post-lab report. b) Bonus: If you are interested, you can try implementing the folded IIR design on the FPGA with top_IIR_fold.v and lab3_IIR_fold_test. The output from the implementation is lab3_IIR_fold_results. c) Please add the RAM IP with write width 8, and name blk_mem_gen_1 , as shown in figure below. d) Note that the 3-input adder in Figure 1 should be replaced by two 2-input adders, as in Figure 2. e) You are required to have the following folding set for the multipliers: {m1, m2, m4, m3}, and for the adders: {a3, a2, a1, ∅ }. The folding orders of input and output are both 0 (you can realize this by regarding the input and output ports as components and adding two folding sets when performing folding: {input, ∅ , ∅ , ∅ }, {output, ∅ , ∅ , ∅ }). f) You may need to do retiming for these folding sets. Please refer to the lectures for the detail of retiming.

ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 8 5 Pre-Lab Submission 1. Please only submit 1 PDF file, containing the following items: a. Copy your code in “unfolded_IIR.v” b. Screenshots of the behavioral simulation of unfolded IIR design. c. Write your observations from the simulation waveform regarding the inputs, output, latencies, intermediate signals etc d. Answers to the following question: What are the pros and cons of unfolding and folding, compared with the original design? 2. Please name the PDF file as “Lab#_PreLab_Section#_LastName_FirstName.pdf” 3. Please submit the PDF file on Teams à Assignments à Lab3 6 Post-Lab Submissions 1. Please only submit 1 PDF file, including the following items: a. Screenshots of the terminal outputs of unfolded IIR design. b. Plot of the data in the unfolded IIR output file. c. Write your observations from the FPGA terminal outputs and the plotted values. d. Screenshots of the behavioral simulation of the folded IIR design. (Graduate students only) 2. Please name the PDF file as “Lab#_PostLab_Section#_LastName_FirstName.pdf” 3. Please submit the PDF file on Teams à Assignments à Lab3