homework 1 solutions v3

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University of Florida *

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5400

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Electrical Engineering

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Apr 3, 2024

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Homework 1 EEE5400 – Future of microelectronics circuits Solutions
All dimensions are in nanometers (nm) Solutions: Mandrel Pitch = 120nm (2 x 60nm) Mandrel CD = 52nm (60 – 8nm) Spacer CD = 8nm 120 52 8 Question 1: Draw the “Top View” of the mandrel mask and spacer Dimension using to pattern Intel 22nm fins. (Hint: You need to look up intel’s Fin Pitch) FIN PATTERNING 60 self-aligned double patterning (SADP) process is used Fin pitch=60nm Fin width=8nm https://en.wikichip.org/wiki/22_nm_lithography_process
All dimensions are in nanometers (nm) Solution: Mandrel Pitch = 84nm 2x 42nm Mandrel CD = 34nm 42 - 8 Spacer CD = 8 nm 84 34 8 Question 2: Draw the “Top View” of the mandrel mask and spacer Dimension using to pattern Intel 14nm fins and gate. (Hint: You need to look up intel’s Fin and gate Pitch) FIN PATTERNING https://en.wikichip.org/wiki/14_nm_lithography_process 42 self-aligned double patterning (SADP) process is used Fin pitch=42nm Fin width=8nm
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All dimensions are in nanometers (nm) Solution: Mandrel Pitch = 140nm 2 x 70nm Mandrel CD = 50nm 70nm – 20nm Spacer CD = 20nm 140 50 20 Question 2: Draw the “Top View” of the mandrel mask and spacer Dimension using to pattern Intel 14nm fins and gate. (Hint: You need to look up intel’s Fin and gate Pitch) GATE PATTERNING https://en.wikichip.org/wiki/14_nm_lithography_process self-aligned double patterning (SADP) process is used gate pitch=70nm gate width=20nm
All dimensions are in nanometers (nm) Mandrel CD = 41nm|Mandrel Pitch = 136nm| Spacer1 CD = 27nm | Spacer 1 pitch=68nm |Spacer2 CD=7nm| Spacer2 pitch=34nm| Question 3: Draw the “Top View” of the mandrel mask and spacer Dimension using to pattern Intel 10nm fins and gate. (Hint: You need to look up intel’s Fin and gate Pitch) FIN PATTERNING SAQP is used here since the fin pitch is 34nm (SAQP need for 40nm to 20nm features). Estimate fin is ~ 7nm in thickness. 7 34 27 68 41 136 Solution: Mandrel pitch = 136 4 x 34 Spacer 2 = 7nm Constrain 1: Mandrel CD + spacer 1 = 68nm Constrain 2: spacer 1+ Spacer 2= 34 => Spacer 2 = 34 - 7 nm = 27nm => Mandrel CD = 68 – 27 = 41nm https://en.wikichip.org/wiki/10_nm_lithography_process
Question 3: 7 34 27 68 41 136 Solution: Mandrel pitch = 136 4 x 34 Spacer 2 = 7nm Constrain 1: Mandrel CD + spacer 1 = 68nm Constrain 2: spacer 1+ Spacer 2= 34 => Spacer 2 = 34 - 7 nm = 27nm => Mandrel CD = 68 – 27 = 41nm
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Question 3: SAQP: need to quickly understand 3 constraints (1) Mandrel 1 pitch (2) Spacer 2 width (3) Spacer 1 width (hard). Need to understand its my next mandrel as apply SADP again to get SAQP (pitch ¼)
All dimensions are in nanometers (nm) Mandrel CD = 36nm Mandrel Pitch = 108nm Spacer CD = 18nm 108 36 18 Question 3: Draw the “Top View” of the mandrel mask and spacer Dimension using to pattern Intel 10nm fins and gate. (Hint: You need to look up intel’s Fin and gate Pitch) GATE Patterning Gate length=18nm Gate pitch=54nm Ref: https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and- core-i3-8121u-deep-dive-review/3 https://en.wikichip.org/wiki/10_nm_lithography_process Solutions: Mandrel Pitch = 108nm (2 x 54nm) Spacer CD = 18nm Mandrel CD = 36nm (54 – 18nm)
Question 4: Explain with support how TSMC patterned fins and gate for the 5nm A14 chips TSMC’s 5nm A14 chips was patterned by using EUV: ASML's NXE:3400C EUV lithography scanners UV light with wavelength of 13.5nm EUV uses reflective optics (i.e. the light is reflected and does not pass through lens or a mask) The gates for TSMC were likely directly pattered using EUV and not using SADP/SAQP techniques See this Ref: https://ieeexplore.ieee.org/document/8993577
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