EXPERIMENT_6

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Apr 3, 2024

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P a g e 1 | 9 EXPERIMENT 6 Binary Adders OBJECTIVES: • Design a 1-bit full adder based on its truth table. • Demonstrate modular design and hierarchy. • Use Vivado simulation tool to test combinational circuits. DISCUSSION: Addition and subtraction are two essential arithmetic functions performed by computers and other digital systems. It is therefore important to understand how to design a circuit to perform such functions. An adder can be 1 or more bits. A 4-bit adder can add two 4-bit unsigned binary numbers. If larger binary numbers are to be added, an adder with more bits is needed. Let’s observe what happens when adding two 4-bit binary numbers: The symbols [A3 A2 Al A0] and [B3 B2 B1 B0] represent 4-bit augend and 4-bit addend, respectively. C0 is the carry bit generated by adding bits A0 and B0. C1 is the carry bit generated from the addition of C0, Al, and B1. C2 and C3 are generated in the same manner, with C3 as the carry-out. The column containing A0 and B0 (the least significant bits) allows for a carry-in from a previous addition, for this example we set it to 0. Each column adds three bits. The implementation of the above process in hardware called a full adder . When we perform this addition, we will start from the least significant bit, and then push the process left one bit at a time. This means that a 1-bit full adder is the basic element of a 4-bit adder and four such elements are needed to construct a 4-bit adder.

P a g e 2 | 9 The 1-Bit Full Adder From the discussion above, we know that a 1-bit full adder should have three inputs: carry-in (C in ), input (A), and input (B). We can determine the number of the output bits by looking at any column in the addition process, say, the column containing C0, A1 and B1. Assume all three bits are 1. Therefore, the result of 1+1+1 is 3 in decimal (base 10) or “11” in binary. The sum requires two bits but S1 is a single bit, so there must be a carry-out to the next column. Each column will produce a sum bit and a carry-out to the next more significant bit position. Therefore, the circuit for the 1-bit full adder should have three inputs: A, B, carry-in (C in ); two outputs: sum bit (S) and carry-out (C out ). The table below shows the truth table for the 1-bit full adder: Input Output C in B A C out S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 By using Boolean algebra, we can derive the following two equations for the sum bit (S) and the carry-out bit (C out ): ࠵? = ࠵? ⊕ ࠵? ⊕ ࠵? ࠵?࠵? ࠵? ࠵?࠵?࠵? = (࠵? + ࠵?)࠵? ࠵?࠵? + ࠵?࠵? The above two equations can be implemented using a 3-input XOR gate, two 2-input AND gates, and two 2-input OR gates.

P a g e 3 | 9 The 4-bit Adder Once we have the 1-bit full-adder (FA), we can use it as a building block in any design that needs to do addition, such as the multi-bit adder in a CPU. In a multi-bit adder, the carry-in (C in ) of the least significant bit (LSB) must be connected to 0 since there is no previous stage . The carry output from the LSB stage (c01) should feed into the second least significant bit. The carry output of second least significant stage (c12) feeds into the next more significant stage as carry input, and so on. The last carry output (C out ) is the most significant bit of the sum. The 4-bit adder block diagram with interconnections between the FA modules is shown in figure below: PROCEDURE: Part 1: The 1-bit Full Adder (BASYS 3 board implementation) 1.) Implement 1-bit Full Adder using VHDL on BASYS 3 board. 2.) Define the entity name as “ full_adder ”, specify the input and output ports as following:

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P a g e 4 | 9 3.) Type the VHDL code for 1-bit Full Adder between begin and end Behavioral as follows: 4.) Use the xdc template from: https://www.xilinx.com/support/documentation/university/Vivado- Teaching/HDL-Design/2015x/Basys3/Supporting%20Material/Basys3_Master.xdc Copy and paste the whole text into your constraints file. Uncomment by deleting the # signs in front of the lines of switches and LEDs that we’re going to use. Modify the port names to match with port names defined in the design source as follows: 5.) Run synthesis, run implementation, and generate bitstream . If running synthesis or implementation failed, double check your design file (.vhd). If bitstream generation failed, double check your constraints file (.xdc) 6.) Program the target board. 7.) Toggle the switches, observe and verify your results. 8.) Fill out the truth tables and answer post-experiment questions.

P a g e 5 | 9 RESULTS: Part 1 With the following input conditions, complete the truth table of 1-bit Full Adder below: C in B A C out S Decimal Value 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Questions: 1.) Attach 2 photos of your BASYS 3 board results showing the following input conditions : • C in = 1, B=0, and A=1 • C in = 1, B=1, and A=1

P a g e 6 | 9 PROCEDURE: Part 2: Building a 4-bit Adder using 4 Full-Adder (FA) Modules (Simulation only) In this part of the experiment, we will show how to perform modular design by building the 4-bit adder using four 1-bit full adder modules . (Ripple-carry adder) 1.) Within the same project, create another design source file with the file name “ ripple_adder ” 2.) Define the entity name as “ ripple_adder ”, specify the input and output ports as following:

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P a g e 7 | 9 3.) Add VHDL code to build a component of “full_adder” as follows. (Note that the component name has to match the entity name in the 1-bit full adder design file you created in Part 1.) 4.) Create a simulation source file without defining any I/O ports as follows:

P a g e 8 | 9 5.) Modify the simulation source file as follows. (Note that component name and unit under test (uut) name i.e. “ripple_adder” have to match the entity name in the design code in Part 2 - Step3.) 6.) Save all changes. Run simulation and observe your results. 7.) Fill out the tables and answer post-experiment questions.

P a g e 9 | 9 RESULTS: Part 2 From your simulation results, complete the table below: Input Output C in A 3 A 2 A 1 A 0 Decimal B 3 B 2 B 1 B 0 Decimal C out S 3 S 2 S 1 S 0 Decimal 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 0 2 0 0 0 1 0 4 0 0 0 1 1 3 0 1 0 1 5 0 0 1 0 0 8 0 0 1 1 0 5 0 1 1 1 7 0 1 1 0 0 12 0 0 1 1 1 7 0 0 1 1 3 0 1 0 0 0 10 0 1 0 1 0 10 0 0 0 1 1 0 1 0 1 1 11 0 1 0 0 1 9 0 1 1 0 8 1 0 0 0 1 17 0 1 1 0 0 12 1 1 0 0 12 1 1 0 0 0 24 0 1 0 1 1 11 0 0 1 1 3 0 1 1 1 0 14 0 1 1 1 1 15 1 1 1 1 15 1 1 1 1 0 30 Hint: 1.) How to convert a 4-bit binary number to its equivalent decimal value (base 10)? If a 4-bit binary number X = “ 1010 ” (i.e. X 3 = 1 , X 2 = 0 , X 1 = 1 , X 0 = 0 ), the equivalent decimal value of X equals ( 1 × 2 & ) + ( 0 × 2 ’ ) + ( 1 × 2 ( ) + ( 0 × 2 ) ) = 8 + 0 + 2 + 0 = 10 2.) If 4-bit adder produces carry-out (C out ), that carry-out bit becomes the Most Significant Bit (MSB) of the sum: ( C *+, × 2 - ) + ( S & × 2 & ) + ( S ’ × 2 ’ ) + ( S ( × 2 ( ) + ( S ) × 2 ) ) Questions: 1.) Attach 2 screenshots of your simulation results showing the waveform from 0 ns to 1000 ns . a. Collapse all the data. b. Expand the data to show all binary values. 2.) Summarize the results in your own words. What did you learn from this experiment? (75 words minimum)

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