Lab 5_ digital stopwatch

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Arizona State University *

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238

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Electrical Engineering

Date

Apr 3, 2024

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docx

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16

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ECE 238 – Computer Logic Design Lab 5: DIGITAL STOPWATCH Section 3: Monday 1:00 – 3:45 pm Name: Jolena Akudago Teammate: Tiresius Johnson Lab 5A VHDL Source Code:
Design Schematic: Simulation Code (Test Bench):
Simulation Waveform:
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Constraints File:
Lab 5B VHDL Source Code: Design Schematic: Simulation Code (Test Bench):
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Simulation Waveform: Constraints File:
Lab 5C VHDL Source Code:
Design Schematic:
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Simulation Code (Test Bench): Simulation Waveform:
Constraints File:
Lab 5D VHDL Source Code:
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Design Schematic:
Simulation Code (Test Bench):
Simulation Waveform: Constraints File: Summary:
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In Lab 5, spanning Projects 5A, 5B, 5C, and 5D, we developed a digital stopwatch using VHDL. Project 5A Frequency Divider : We started with the frequency divider, a component that downscaled the FPGA's system clock to a manageable 1Hz clock. This slower clock pace was crucial, serving as the “heartbeat” for our stopwatch, ensuring it ticks once per second. Project 5B 4-Bit Counter: Next, we introduced a 4-bit counter, the core of our stopwatch's timekeeping function. This counter increments once every second, courtesy of the 1Hz clock from Project 5A. The counter's backbone is a series of D-Flip-Flops, synchronized to this slow clock. D-Flip-Flops are digital devices that capture the value of their input at the moment of the clock's rising or falling edge and maintain this value until the next clock event. In this part of the lab, they serve as memory elements, each storing a bit of the current count. As the clock ticks, the counter's state progresses, effectively measuring elapsed time in seconds. Project 5C 1-Digit Numerical Display: With the counting mechanism in place,we created a physical display that displaying the counted seconds. A decoder transforms the 4-bit counter output into a signal for a 7-segment display. This visual representation is the stopwatch's interface, where binary count values are translated into decimal digits. Project 5D Top Module Integration: Finally, we brought all the pieces together in the top module, integrating the frequency divider, counter, and display decoder. Challenges Encountered: When creating our design code for our display decoder, we ran into issues regarding our if/else statements. They were not syntaxliy correct and had to be fixed in a latter lab. Also just remembering to change the time frame for our board vs seeing it on our waveform. Helpful Hints: A solid grasp of component interaction and precise timing. Also these labs are starting to really build on each other so having a good understanding of past labs will be very helpful. Suggested improvements: We don’t have any suggestions at the moment, but I will take advantage of this section in future labs.