QUIZ-6

ASM with MSI Devices 1. Complete the ROM Table based on the final ASM chart shown in #1, and thecircuit diagram shown in #2.2. Complete the EPROM Programming Table based on the ROM Table.

3. Given the following memory chip configurations find the requested information: EPROM with 14 address lines (pins) and 8 data lines (pins). What is the chip capacity (include units)? What is the chip organization? Volatile or Non-volatile (circle one) SRAM with 18 address lines (pins) and 4 data lines (pins). What is the chip capacity (include units)? What is the chip organization? Volatile or Non-volatile (circle one) NV-RAM with 10 address lines (pins) and 4 data lines (pins). What is the chip capacity (include units)? What is the chip organization? Volatile or Non-volatile (eircle one) DRAM with 13 address lines (pins) and 1 data lines (pins). What is the chip capacity (include units)? What is the chip organization? Volatile or Non-volatile (circle one) If the memory chip below is used in a system with a 16-bit address bus, then address lines A13 – A15 would need to be decoded externally. Find the address range for each of the possible decoding combinations (000, 001, 010 ... 111)…

Q1: B- Fill out the following blanks: .3-The first 1- Bus-snooping is used for.......2- Two examples of status-flag registers.... computer that used 32-bit microprocessor was......... 4- The inter-processor communication via .5- If a system uses 16-bit address bus, it can reach memory locations up to.......6- Cache memory uses two algorithms for writing... 7- SRAM is better than DRAM due to.......

Using a combination of shift registers and latches explain how a small number ofmicrocontroller I/O pins can be used to read from or write to a large number of digitalsignal lines. Illustrate your answer. What is the main disadvantage of this I/O expansionapproach?

i need the answer quickly

3 Consider the combinational circuit shown below. The propagation delay for each unit is indicated in ns. Assume all other delays are zero. 8 ns C(x,y) X 10 ns 10 ns y - 7 ns 5 ns 5 ns a) What is the latency and throughput of the circuit as shown? b) Indicate where storage registers should be placed to create a two-stage pipeline with maximum throughput. c) What is the latency and throughput of the two-stage pipeline in part b? d) What is the best throughput that can be obtained by pipelining? How many stages would this pipeline have?

Assume that memory location $c100 holds a data byte =$37, [ACCA]= $B8 and [ACCB]=$FE. For each of the following instructions determine the resultant content of ACCA or ACCB. (a) ANDA $C100 (b) ANDA #$05 ORAB #$EE (c) (d) CLR B (e) NEGA (f) DECB (g) ASLA (h) LSRB (i) EORA #$E4 (G) ROR A

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Q3/(A) False OR True 1- A0-0 and BHE-1 are used as low bank-select signal: 2-AX is 2234 H after executing the following instruction: AAS. If AX-2234H. 3-IP register holds the offset address of the next instruction to be executed. 4- The XLAT instruction in 8086 assembly language is used to perform arithmetic operations between two memory operands. 5- Bus interface unit is responsible form