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Date
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EECS 16B
Designing Information Systems and Devices II
UC Berkeley
Fall 2023
Homework 3
This homework is due on Friday, February 10, 2023 at 11:59PM. Self-
grades and HW Resubmissions are due the following Friday, February
17, 2023 at 11:59PM.
1. NAND Circuit
Let us consider a NAND logic gate. This circuit implements the boolean function
(
A
·
B
)
. The
·
stands
for the AND operation, and the
stands for NOT; combining them, we get NAND!
P
A
P
B
N
B
V
B
N
A
V
A
V
out
V
DD
Figure 1:
NAND gate transistor-level implementation.
V
tn
and
V
tp
are the threshold voltages for the NMOS and PMOS transistors, respectively. Assume that
V
DD
>
V
tn
,
|
V
tp
|
>
0.
(a)
Label the gate, source, and drain nodes for the NMOS and PMOS transistors (please redraw
the circuit).
Solution:
As a convention throughout the course, we will draw NMOS transistors with their
source at the bottom (and drain at the top). On the other hand, PMOS transistors will have their
source at the top. Therefore, the drains are at the top of
N
A
(connected to
V
out
) and the top of
N
B
(connected to
N
A
). The sources are at the bottom of
N
A
(connected to
N
B
) and the bottom of
N
B
(connected to ground). The gate terminal of
N
A
is connected to
V
A
; the gate of
N
B
is connected
to
V
B
.
For the PMOS transistors, the source is at the top of
P
A
and
P
B
(connected to
V
DD
). The drain is
at the bottom of
P
A
and
P
B
(connected to
V
out
). The gate terminal of
P
A
is connected to
V
A
; the
gate of
P
B
is connected to
V
B
.
1
EECS 16B Homework 3
2023-09-18 10:02:32-07:00
(b) If
V
A
=
V
DD
and
V
B
=
V
DD
,
which transistors act like open switches? Which transistors act
like closed switches? What is
V
out
?
Solution:
P
A
and
P
B
are off (open switches).
N
B
and
N
A
are on (closed switches).
V
out
=
0V
because it is connected to ground through a closed circuit consisting of
N
A
and
N
B
(and detached
from
V
DD
).
(c)
If
V
A
=
0
V
and
V
B
=
V
DD
, what is
V
out
?
Solution:
P
B
and
N
A
are off (open switches).
P
A
and
N
B
are on (closed switches).
V
out
=
V
DD
because it is connected to
V
DD
through a closed circuit consisting of
P
A
(and detached from
ground, since
both N
A
and
N
B
must be closed for
V
out
to be connected to ground).
(d)
If
V
A
=
V
DD
and
V
B
=
0
V
, what is
V
out
?
Solution:
P
A
and
N
B
are off (open switches),
P
B
is on (closed switch). So,
V
out
=
V
DD
because it
is connected to
V
DD
through a closed switch.
(e)
If
V
A
=
0
V
and
V
B
=
0
V
, what is
V
out
?
Solution:
N
B
is off, creating an open circuit.
P
A
and
P
B
are on, creating a closed circuit.
V
out
=
V
DD
because it is connected by closed circuit to
V
DD
.
(f)
Write out the truth table for this circuit.
V
A
V
B
V
out
0
0
0
V
DD
V
DD
0
V
DD
V
DD
Solution:
V
A
V
B
V
out
0
0
V
DD
0
V
DD
V
DD
V
DD
0
V
DD
V
DD
V
DD
0
© UCB EECS 16B, Fall 2023.
All Rights Reserved. This may not be publicly shared without explicit permission.
2
EECS 16B Homework 3
2023-09-18 10:02:32-07:00
2. Hambley P4.61
A DC source is connected to a series RLC circuit by a switch that closes at
t
=
0, as shown in Figure
2
.
The initial conditions are
i
(
0
+) =
0 and
v
C
(
0
+) =
25. Write the differential equation for
v
C
(
t
)
. Solve
for
v
C
(
t
)
given that
R
=
80
\YX
.
−
+
50 V
t
=
0
L
=
2 mH
R
C
=
5 µF
+
−
v
C
(
t
)
i
(
t
)
Figure 2:
P4.61
Solution:
We can apply KVL to the circuit to obtain:
50
=
v
L
(
t
) +
v
R
(
t
) +
v
C
(
t
)
(1)
=
L
d
i
(
t
)
d
t
+
i
(
t
)
R
+
v
C
(
t
)
(2)
=
L
d
i
(
t
)
d
t
+
RC
d
v
C
(
t
)
d
t
+
v
C
(
t
)
(3)
Now, we have that
L
d
i
(
t
)
d
t
=
L
d
d
t
C
d
v
C
(
t
)
d
t
=
LC
d
2
v
C
(
t
)
d
t
2
. Plugging this in, we get
LC
d
2
v
C
(
t
)
d
t
2
+
RC
d
v
C
(
t
)
d
t
+
v
C
(
t
) =
50
(4)
d
2
v
C
(
t
)
d
t
2
+
R
L
d
v
C
(
t
)
d
t
+
1
LC
v
C
(
t
) =
50
LC
(5)
We have a second order differential equation, so our solution will be of the form
v
C
(
t
) =
v
C
P
(
t
) +
v
C
H
(
t
)
, where
v
C
P
(
t
)
is the particular solution and
v
C
H
(
t
)
is the homogeneous solution. Here, we
have a DC forcing function (i.e.,
f
(
t
) =
50
LC
). Hence, the particular solution would be the solution if
we replaced inductors with short circuits and capacitances with open circuits. This yields
v
C
P
(
t
) =
50.
To find
α
and
ω
0
, we can pattern match
ω
0
=
q
1
LC
=
10
4
and 2
α
=
R
2
L
=
⇒
α
=
R
2
L
=
2
×
10
4
from
Note 5. Since
α
>
ω
0
, the homogeneous solution will be of the form
v
C
H
(
t
) =
K
1
e
s
1
t
+
K
2
e
s
2
t
(6)
where
s
1
=
−
α
+
q
α
2
−
ω
2
0
=
−
2679.49 and
s
2
=
−
α
−
q
α
2
−
ω
2
0
=
−
37320.5. Hence, the final
solution is of the form
v
C
(
t
) =
v
C
P
(
t
) +
v
C
H
(
t
) =
50
+
K
1
e
s
1
t
+
K
2
e
s
2
t
(7)
To find
K
1
and
K
2
, we can utilize the fact that
v
C
(
0
) =
25 and
d
v
C
(
t
)
d
t
|
t
=
0
=
i
(
0
)
C
=
0. Plugging these in,
we get the following system:
v
C
(
0
) =
25
=
50
+
K
1
+
K
2
(8)
© UCB EECS 16B, Fall 2023.
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EECS 16B Homework 3
2023-09-18 10:02:32-07:00
d
v
C
(
t
)
d
t
|
t
=
0
=
0
=
s
1
K
1
+
s
2
K
2
(9)
Solving this system of equation yields
K
1
=
−
26.93 and
K
2
=
1.93. Hence, the final answer is
v
C
(
t
) =
50
+ (
−
26.93
)
e
−
2679.49
t
+ (
1.93
)
e
−
37320.5
t
(10)
© UCB EECS 16B, Fall 2023.
All Rights Reserved. This may not be publicly shared without explicit permission.
4
EECS 16B Homework 3
2023-09-18 10:02:32-07:00
3. Hambley P4.64
Consider the circuit shown in Figure
3
, with
R
=
25
\YX
.
1 A
t
=
0
R
L
=
10 µH
i
L
(
t
)
C
=
1000 pF
+
−
v
(
t
)
Figure 3:
P4.64
(a) Compute the undamped resonant frequency,
ω
0
, and
α
.
Solution:
From KCL, we have
1
=
i
R
(
t
) +
i
L
(
t
) +
i
C
(
t
)
(11)
=
v
(
t
)
R
+
i
L
(
t
) +
C
d
v
(
t
)
d
t
(12)
Taking derivatives on both sides, we get
C
d
2
v
(
t
)
d
t
2
+
1
R
d
v
(
t
)
d
t
+
d
i
L
(
t
)
d
t
=
0
(13)
We also know that
v
(
t
) =
L
d
i
L
(
t
)
d
t
. Plugging this in, we get
C
d
2
v
(
t
)
d
t
2
+
1
R
d
v
(
t
)
d
t
+
1
L
v
(
t
) =
0
(14)
d
2
v
(
t
)
d
t
2
+
1
RC
d
v
(
t
)
d
t
+
1
LC
v
(
t
) =
0
(15)
Pattern matching to Note 5, we get
ω
0
=
q
1
LC
=
1
×
10
7
and 2
α
=
1
RC
=
4
×
10
7
=
⇒
α
=
2
×
10
7
. Hence, it is an overdamped circuit (
α
>
ω
0
).
(b) The initial conditions are
v
(
0
+) =
0 and
i
L
(
0
+) =
0. Show that this requires
v
′
(
0
+) =
10
9 V
s
.
Solution:
We still must satisfy KCL at
t
=
0
+
, so we have
1
=
i
R
(
0
+) +
i
L
(
0
+) +
i
C
(
0
+)
(16)
=
v
(
0
+)
R
+
i
L
(
0
+) +
Cv
′
(
0
+)
(17)
=
Cv
′
(
0
+)
(18)
This leaves us with
v
′
(
0
+) =
1
C
=
10
9 V
s
.
(c) Find the particular solution for
v
(
t
)
.
Solution:
To find the particular solution, we first notice that the forcing function is
f
(
t
) =
0
which is a constant.
Hence, we can replace capacitors with open circuits and inductors with
short circuits. If we were to do this, all of the current flows through the branch with the inductor
and the particular solution is
v
P
(
t
) =
0.
© UCB EECS 16B, Fall 2023.
All Rights Reserved. This may not be publicly shared without explicit permission.
5
EECS 16B Homework 3
2023-09-18 10:02:32-07:00
(d) Find the general solution for
v
(
t
)
, including the numerical values of all parameters.
Solution:
Since
α
>
ω
0
, the homogeneous solution will be of the form
v
C
(
t
) =
K
1
e
s
1
t
+
K
2
e
s
2
t
(19)
where
s
1
=
−
α
+
q
α
2
−
ω
2
0
=
−
2.68
×
10
6
and
s
2
=
−
α
−
q
α
2
−
ω
2
0
=
−
3.73
×
10
7
. Since the
particular solution
v
P
(
t
) =
0, we have that
v
(
t
) =
K
1
e
s
1
t
+
K
2
e
s
2
t
(20)
Now, we will use our initial conditions of
v
(
0
) =
0 and
v
′
(
0
) =
10
9
. Plugging these in, we get
the following system of equations:
v
(
0
) =
0
=
K
1
+
K
2
(21)
v
′
(
0
) =
10
9
=
s
1
K
1
+
s
2
K
2
(22)
Solving the system of equations yields
K
1
=
28.89 and
K
2
=
−
28.89. Thus, the final answer is
v
(
t
) =
28.89e
(
−
2.68
×
10
6
)
t
−
28.89e
(
−
3.73
×
10
7
)
t
(23)
© UCB EECS 16B, Fall 2023.
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EECS 16B Homework 3
2023-09-18 10:02:32-07:00
4. Phasor-Domain Circuit Analysis
The analysis techniques you learned previously in 16A for resistive circuits are equally applicable for
analyzing circuits driven by sinusoidal inputs in the phasor domain. In this problem, we will walk
you through the steps with a concrete example.
Consider the following circuit where the input voltage is sinusoidal. The end goal of our analysis is
to find an equation for
V
out
(
t
)
.
−
+
V
s
(
t
)
i
R
(
t
)
R
+
−
V
R
(
t
)
C
i
C
(
t
)
L
+
−
V
out
(
t
)
i
L
(
t
)
The components in this circuit are given by:
V
s
(
t
) =
10
√
2 cos 100
t
−
π
4
(24)
R
=
5
\YX
(25)
L
=
50 mH
(26)
C
=
2 mF
(27)
(a)
Give the amplitude
V
0
, input frequency
ω
, and phase
ϕ
of the input voltage
V
s
.
Solution:
A sinusoid takes the form
v
(
t
) =
V
0
cos
(
ω
t
+
ϕ
)
. Given
V
s
(
t
)
, we find:
V
0
=
10
√
2V
(28)
ω
=
100
rad
s
(29)
ϕ
=
−
π
4
rad
(30)
(b) Transform the circuit into the phasor domain.
What are the impedances of the resistor, capaci-
tor, and inductor? What is the phasor
e
V
S
of the input voltage
V
s
(
t
)
?
Solution:
Z
L
=
j
ω
L
=
j5
\YX
(31)
Z
C
=
1
j
ω
C
=
−
j5
\YX
(32)
Z
R
=
R
=
5
\YX
(33)
e
V
s
=
|
V
s
|
e
j
∠
V
s
=
10
√
2e
−
j
π
4
(34)
© UCB EECS 16B, Fall 2023.
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7
EECS 16B Homework 3
2023-09-18 10:02:32-07:00
(c) Use the circuit equations to
solve for
e
V
out
, the phasor representing the output voltage.
Solution:
The phasor representation of the circuit is shown below:
Where
e
I
R
=
e
V
S
−
e
V
out
R
(35)
e
I
L
=
e
V
out
j
ω
L
(36)
e
I
C
=
e
V
out
·
j
ω
C
(37)
Rewriting the current relation in terms of voltage phasors gives:
e
V
S
−
e
V
out
R
=
e
V
out
j
ω
L
+
e
V
out
·
j
ω
C
(38)
Substituting the component values in the above equation we get
e
V
S
−
e
V
out
5
=
e
V
out
5j
+
e
V
out
·
j
5
(39)
=
e
V
out
5j
−
e
V
out
5j
(40)
=
0
(41)
Which gives:
e
V
out
=
e
V
S
(42)
We found that
e
V
out
=
e
V
S
because this circuit is in resonance; i.e., the capacitor and inductor
have the exact values that cause current and voltage to endlessly oscillate between them at this
frequency. If we chose a different value for
ω
with these same component values, the circuit
would not be in resonance and
e
V
out
and
e
V
S
would no longer be equal.
One may think that this answer seems weird.
For
e
V
out
to equal
e
V
S
means that no current is
flowing through the resistor. This means that somehow, the impedance of the parallel
L
and
C
combination would have to be infinity. Let’s check what that is:
Z
L
∥
Z
C
=
(
j5
)
·
(
−
j5
)
j5
+ (
−
j5
)
= +
ª§¦ª
(43)
© UCB EECS 16B, Fall 2023.
All Rights Reserved. This may not be publicly shared without explicit permission.
8
EECS 16B Homework 3
2023-09-18 10:02:32-07:00
Wow! Indeed it is infinity. This shows something counterintuitive that can occur with phasors
and impedances. For resistors, one may think that parallel connections always lower the resis-
tance. However, since imaginary impedances can be positive imaginary and negative imaginary,
a parallel connection can make the impedance bigger or smaller. The same kind of counterin-
tuitive behavior is also possible for series combinations. Resistors in series always increase the
resistance. But the same L and C in series can combine to have a zero impedance at the natural
frequency.
If one wants to know why
something divided by 0
is
ª§¦ª
in the complex plane, read this Wiki
article:
Riemann Sphere
.
This is another facet of complex analysis, and why engineers were
drawn to it when modeling physical systems for design purposes.
© UCB EECS 16B, Fall 2023.
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EECS 16B Homework 3
2023-09-18 10:02:32-07:00
5. Hambley P6.55
Consider the circuit shown in Figure
4
. The input signal is given by
v
in
(
t
) =
5
+
5 cos
(
2000
π
t
)
(44)
Find an expression for the output
v
out
(
t
)
in steady-state conditions.
−
+
v
in
(
t
)
C
=
1 µF
R
=
1000
2
π
\YX
Figure 4:
P6.55
(HINT: Use superposition. That is, find v
out,1
(
t
)
which is the output voltage if the input is v
in,1
(
t
) =
5
, and
then find v
out,2
(
t
)
which is the output voltage if the input is v
in,2
(
t
) =
5 cos
(
2000
π
t
)
. What is v
out
(
t
)
in
terms of v
out,1
(
t
)
and v
out,2
(
t
)
?)
Solution:
The input signal is given by
v
in
(
t
) =
5
+
5 cos
(
2000
π
t
)
(45)
We can find
e
V
out
as a function of
ω
and
e
V
in
, then apply superposition. Applying the fact that
Z
C
=
1
j
ω
C
and
Z
R
=
R
, we can use the voltage divider formula to write
e
V
out
=
Z
R
Z
R
+
Z
C
e
V
in
(46)
=
R
R
+
1
j
ω
C
e
V
in
(47)
=
j
ω
RC
j
ω
RC
+
1
e
V
in
(48)
Now, let’s first consider
v
in,1
(
t
) =
5 as per the hint. We have
e
V
in,1
=
5e
j0
, and the corresponding
frequency is
ω
=
0 (we can write
v
in,1
(
t
) =
5
=
5 cos
(
0
·
t
+
0
)
). Thus, plugging into eq. (48), we
get
e
V
out,1
=
j0
j0
+
1
=
0. Hence,
v
out,1
(
t
) =
0. Next, we consider
v
in,2
(
t
) =
5 cos
(
2000
π
t
)
. We have
e
V
in,2
=
5e
j0
, and the corresponding frequency is
ω
=
2000
π
. Thus, plugging into eq. (48), we get
e
V
out,2
=
j
(
2000
π
)
RC
j
(
2000
π
)
RC
+
1
·
5. Plugging in for the provided values of
R
and
C
, we obtain
e
V
out,2
=
5
j
1
+
j
. To
convert this to polar form, we compute the magnitude and phase as follows:
e
V
out,2
=
5
j
1
+
j
=
5
|
j
|
|
1
+
j
|
=
5
√
2
(49)
∠
e
V
out,2
=
∠
5j
1
+
j
=
∠
(
5j
)
−
∠
(
1
+
j
) =
π
2
−
π
4
=
π
4
(50)
© UCB EECS 16B, Fall 2023.
All Rights Reserved. This may not be publicly shared without explicit permission.
10
EECS 16B Homework 3
2023-09-18 10:02:32-07:00
Thus, we can equivalently write
e
V
out,2
=
5
√
2
e
j
π
4
. Converting back into time domain, we get
v
out,2
(
t
) =
5
√
2
cos
(
2000
π
t
+
π
4
)
. Now, we can apply superposition to find
v
out
(
t
)
. Since we decomposed the
input voltage as a sum of its components, we have
v
out
(
t
) =
v
out,1
(
t
)
|
{z
}
0
+
v
out,2
(
t
)
|
{z
}
5
√
2
cos
(
2000
π
t
+
π
4
)
=
5
√
2
cos 2000
π
t
+
π
4
(51)
Contributors:
• Neelesh Ramachandran.
• Kumar Krishna Agrawal.
• Lev Tauz.
• Varun Mishra.
• Regina Eckert.
• Geoffrey Négiar.
• Antroy Roy Chowdhury.
© UCB EECS 16B, Fall 2023.
All Rights Reserved. This may not be publicly shared without explicit permission.
11
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20LSB
Q2
03MSB
clk
clk
clk
clk
clk
rst
rst
rst
rst
wl
w2
clk QB
cik_by_11
rst
rst
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