Bailey Davidson DAT 260 Module Three Assignment

True or False: 1. A 16 bit data word will require a minimum of 21 bits of storage space if Hamming code error detection is implemented. 2. When writing data to a memory storage device, the first lines to be set are the data lines 3. An octal counter requires a minimum of four JK flipflops 4. In a microprocessor-based system, Dynamic Ram access times are longer than Static RAM because of the refresh requirement. 5. The clock period of the internal clockof a logic monitor must typically be longer than the clock period of the system being monitored.   6. Dynamic RAM is typically found in the Level I and Level II cache of a microprocessor.

Question iii please help......

Explain the arithmetic operations in binary number system and how code conversion is done between binary and decimal numbers.

Plz solve within 40min I vill give definitely upvote and vill give positive feedback thank you sir

QUESTION i please help........

The numbers from 0-9 and a no characters is the Basic 1 digit seven segment display * .can show False True In a (CA) method of 7 segments, the anodes of all the LED segments are * "connected to the logic "O False True Some times may run out of pins on your Arduino board and need to not extend it * .with shift registers True False

29) Write an assembly language program in 8086 microprocessor to find square root of a number. 30) Write an assembly language program in 8086 microprocessor to reverse 16 bit number using 8 bit operation. Assume 16 bit number is stored at memory location 2050 and 2051. 31) Write an assembly language program in 8086 microprocessor to divide a 16 bit number by an 8 bit number. Assumption – Initial value of each segment register is 00000. - Calculation of physical memory address – Memory Address = Segment Register * 10(H) + offset, %3D where Segment Register and Offset is decided on the basis of following table.

What range of decimal integers can be represented by a. three-bit binary numbers; b. three-digit octal numbers; c. three-digit hexadecimal numbers?

What are ways to speed up ripple adders? Mark all that apply. Use faster logic gates. a. Eliminate the output carry. b. Use the principle of carry lookahead. C. Use only multiplexers. d. None of the others are ways to speed up ripple adders. е. Lf. Design for the specific length of the input binary numbers.

1) Is it a Mealy machine or Moore machine? 2) Derive simplified expressions for Output z, and next state FF outputs y1+ and y2+ in terms of input w, and present state y1 and y2. Simplify using Boolean manipulation. You need not name specific Boolean properties/Theorems used. Leave final answers in simplest SoP/PoS forms. 3) Derive its encoded State-Transition Table. 4) Using the encoded State-Transition Table from part c, derive the symbolic state-transition table. Define your states. Use S0, S1, S2, and so on for state names. 5) Draw state diagram with all states and all transitions shown clearly. 6) What sequence of input values on wire w is detected by this circuit?

a) Convert the decimal number - 239 into a signed binary number using (1) sign-magnitude method (2) 1's complement method (3) 2's complement method b) If the above decimal number is positive , that is + 239, then convert it to a signed binary number using 1 's complement method c) Do the following binary subtraction: 101111111.01111- 001011010.10110 d)Explain Types of RAM?

dont use others answers  show your work step by step short answer Suppose we are given the following subset of binary words, created for a 7-bit memory word with one parity bit: 11100110, 00001000, 10101011, and 11111110. Does this code use even or odd parity? Explain in 1-2 sentences.

Problem_#08] For the 4-bit parity generator shown, determine the output. It this circuit generating even or odd parity? Bit time Ao A1 A2 A3

Procedure: 1. Design an even/odd parity generator for 4-bit data. 2. Design a parity checker circuit for a 4-bit data. 3. Design a logic circuit for a 3-bit message to be transmitted with an even parity bit. 4. Four data bits are to be transmitted. Design a parity bit generator to give an o/p of 'l' if the number of logic l's in the message is: (i) odd; (ii) even.

Q1) Write the assembly language instructions required to convert negative numbers to positive numbers, for a block of data of size 2kbytes stored at starting address: 6A000H in the data segment, each of these numbers is an 8-bit signed number.