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Feb 20, 2024

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Page 1 of 2 ECE 5484 ■ Spring 2022 ■ Homework 3 ECE 5484, Homework 3 1. How many bits are required to address a 4M × 16 main memory if a) Main memory is byte-addressable? 4 x 2 20 x 2 = 2 2 x 2 20 x2 1 = 8M = 8388608 = 2 23 = 23 byte- addressable. b) Main memory is word-addressable? (For part b, assume a 16-bit word.) 4 x 2 20 = 2 2 x 2 20 = 4194304 = 4 22 = 22 word-addressable. 2. You want to use 256 x 8 RAM chips to provide a memory capacity of 4096 bytes. a) How many chips will you need?  Total memory capacity: 4096 = 2 12  Each RAM chip memory capacity: 256 = 2 8  Or 4096 ÷ 256 = 16 Result: 2 12 -2 8 =2 4 = 16 chips needed . b) How many bits will each address contain? Since the total memory is 4096 = 2 12 , therefore each address consists of 12 bits. c) How many address lines must go to each chip? Since each RAM chip contain a memory is 256 = 2 8 , therefore we need 8 address lines to go to each chip. d) How many address lines must be decoded for the chip select inputs? In other words, specify the size of the decoder. Since there are in total 16 chips (16 = 2 4 ) we need 4 address lines for the chip select inputs. 3. A digital computer has a memory unit with 40 bits per word. The instruction set consists of 165 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in one word of memory. a) How many bits are needed for the opcode? Since 2 7 = 128 and 2 8 = 256, therefore we need about the 8 bits to have enough space for 165 different operations resulting on opcode of 8 bits . b) How many bits are left for the address part of the instruction? 40 – 8 = 32 bits remained for the address.

Page 2 of 2 ECE 5484 ■ Spring 2022 ■ Homework 3 c) What is the maximum allowable size for memory? The maximum allowable size for memory is 2 32 bytes or 4294697296 bytes. d) What is the largest unsigned binary number that can be accommodated in one word of memory? The largest unsigned binary number that can be accommodated in one word of memory is 2 40 -1 or 1099511627775. 4. Section 4.10 of the text provides an example of the execution of a simple MARIE program. For this problem, you are to complete a similar example for a different program. In particular, for the MARIE program given below, you are to complete the equivalent of Figure 4.14, but for the program below. You do not need to show how the “Halt” instruction is executed. Specify values in PC, IR, MAR, MBR, and AC in hexadecimal. A template for your answer is provided as a Microsoft Word file that is included with this assignment on Canvas. You are to incorporate your answer for this problem into your submission for the homework assignment so that you submit only one PDF file for the entire assignment. The program is as follows. Note that this table is the equivalent of Table 4.3 in the textbook, only for a different program. Hex Addre ss Instructio n Binary Contents of Memory Address Hex Contents of Memory 10 0 Load 105 0001 0001 0000 0101 110 5 10 1 Subt 104 0100 0001 0000 0100 410 4 10 2 Store 104 0010 0001 0000 0100 210 4 10 3 Halt 0111 0000 0000 0000 700 0 10 4 00A3 0000 0000 1010 0011 00A 3 10 5 00F3 0000 0000 1111 0011 00F 3 (a) Load 105 Step RTN PC IR MAR MBR AC (initial values) 100 ― ― ― ― Fetch MAR ← PC 100 ― 100 ― ― IR ← M[MAR] 100 1105 100 ― ― PC ← PC + 1 101 1105 100 ― ― Decode MAR ← IR[11-0] 101 1105 105 ― ― (Decode IR[15-12]) 101 1105 105 ― ―

Page 3 of 2 ECE 5484 ■ Spring 2022 ■ Homework 3 Get operand MBR ← M[MAR] 101 1105 105 00F3 ― Execute AC ← MBR 101 1105 105 00F3 00F3 (b) Subt 104 Step RTN PC IR MAR MBR AC (initial values) 101 1105 105 00F3 00F3 FETCH MAR ← PC 101 1105 101 00F3 00F3 IR ← M[MAR] 101 4104 101 00F3 00F3 PC ← PC + 1 102 4104 101 00F3 00F3 DECODE MAR ← IR[11-0] 102 4104 104 00F3 00F3 (DECODE IR[15-12] 102 4104 104 00F3 00F3 GET OPERAND MBR ← M[MAR] 102 4104 104 00A3 00F3 EXECUTE AC ← AC – MBR 102 4104 104 00A3 0050 (c) Store 104 Step RTN PC IR MAR MBR AC (initial values) 102 4104 104 00A3 0050 FETCH MAR ← PC 102 4104 102 00A3 0050 IR ← M[MAR] 102 2104 102 00A3 0050 PC ← PC + 1 103 2104 102 00A3 0050 DECODE MAR ← IR[11-0] 103 2104 104 00A3 0050 (DECODE IR[15-12] 103 2104 104 00A3 0050 GET OPERAND (NOT NECESSARY) 103 2104 104 00A3 0050 EXECUTE MBR ← AC 103 2104 104 0050 0050 M[MAR] ← MBR 103 2104 104 0050 0050 5. Scavenger Hunt: Two pioneers of early computers and computer organization were Howard H. Aiken and John von Neumann. Answer the questions below regarding Aiken and von Neumann. Cite sources used for your answers. a. Is Aiken or is von Neumann associated with the so-called Princeton architecture? The Princeton architecture, also known as the Von Neumann computer architecture is associated the mathematician and psychist John von Neumann in which he developed in 1945 (Rosenberg, 2017) . b. Is Aiken or is von Neumann associated with the so-called Harvard architecture? The Harvard architecture is associated with the works made by Howard H. Aiken in which also collaborated with the design of the electromechanical Harvard Mark I calculator, also known as the Automatic Sequence Controlled Calculator, or ASCC), and built by IBM Corporation in 1944 (Smith, 1988) .

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Page 4 of 2 ECE 5484 ■ Spring 2022 ■ Homework 3 c. In your own words, what is the key feature of a Princeton architecture computer compared to the Harvard architecture? The key feature of a Princeton architecture computer compared to the Harvard architecture is that Princeton architecture utilize a single bus for data and program instructions in which the operation of fetching and execution cycle must be orchestrated one at the time compared with a Harvard architecture that has separated buses for data and program instructions respectively in which allow the operation of fetching and execution cycle in parallel (Tan & Jiang, 2019) . d. Does the MARIE architecture owe more to Aiken or von Neumann? In your own words, briefly justify your answer. MARIE architecture owe more to von Neumann model because exhibits von Neumann architecture design including shared memory (for data and program storage), Control unit, ALU, and registers (Null & Nobur, 2018) . References Null, L., & Nobur, J. (2018). Essentials of Computer Organization and Architecture, 5th Edition. Jones & Bartlett Learning. Rosenberg, J. (2017). Security in embedded systems. In A. Vega, P. Bose, & A. Buyuktosunoglu, Rugged Embedded Systems (pp. 149-205). Morgan Kaufmann. Smith, R. E. (1988). A Historical Overview of Computer Architecture. Annals of the History of Computing, 10 (4), 277 - 303. doi:10.1109/MAHC.1988.10039 Tan, L., & Jiang, J. (2019). Digital Signal Processing: Fundamentals and Applications, 3rd Edition. Academic Press.