In_Class_Homework_Module_4_Spring_2014_Solutions

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ECE 270 In-Class Homework for Module 4 — No. 1 Introduction to Digital System Design Monday, April 7, 2014 Spring 2014 Solve all possible 2-bit Radix subtraction problems. Determine how the condition codes (C,Z,N,V) are set for each case. 11 ¢n Wty 116 ) 11y o 11 (- —00 (o) 1 -01 -+ o 1 0«{;2} a1 11 _p oo 0 L ) sl |y W + T L0 L0 100 C = i 7 = i C = fi 7 o= E = e 2 o= _9_ = _(Z_ Z = _J__ N = I VvV = _O_- N = i_ VvV = Q_ = i V = fi = _Q Vv = g 10 (-9 lo, 10 (g 10 10 () (o 10 (5 (o - 00 A(\()} V- 01 - (+1) |0 1 Ov{;f;fl 01 11 -1y o° 2 ol I | il (-2 flfé 1,0 4,00 o C = _Q_ Z = _Q_ C = _@_ 4 = {/_} = __O_ 2 = _l_ = _L_ 7 o= _(_7_ N=lv=0ln=0v=_lln=0v=0ln=1v=0 01 («) o) 01 (1) o] 01 (+) of 01 (+) 0] =00 () = 01-() 1 =10y ol 11y oo ()l o)+l 09 + 1 Gy +! C = _0_ 7% = ;O;_ C = Q Z = L = L o= fi = -(_ Z = i N = ;(E_ V = g N = _O_ VvV = ;Q; = _l_ V = i_ = !_ VvV = _L 0 0 (o) 0o 00 (o) 00 00 (o) 06 00 (0 00 - 0 0 (o) % - 0 1;Qfim o) 10 ’(“i> 0| 11 m(fi\:) O% OREAR SO )+ d () ® $00 O | D 00 C = i Z = _E_— C = _\_ 7z = i = _l_ % o= i = L 7 o= _O; N = _O_ V = _Q_ N = _l_ Vv = _9“ = _L vV = l = __?0;. V = ;O;,,_
ECE 270 Introduction to Digital System Design Spring 2014 - In-Class Homework for Module 4 — No. 2 Wednesday, April 9, 2014 Complete the missing entries in the “condition code generation chart,” below, and derive the function for “A less than or equal to B” (“ALEB”) in its simplest form. A1l Ao (A)|B1|Bg|(B) ? C|Z|N|V olololo]olo|@mw=@]ol1/0]0 ML S 00|00 [1[+1]A)<B)|||0]} 0 O fl o% O v oloflol1]lol-2]®m>m@|1]0]1]1 N = ololol1][1][1|®m>®]|1]0]0]0 L d é,?V o|1|+1|o]o|of@>®]|o|ojo]0 37% 7};’3 1:% “{»} 0| 1|+1]0[1[+1|(A)=(B)|0]1]0]0| N H— IIWW\ ol1|+|[1]o]2]@)=@®]|1]0]1]1 @ Al v O l1|+1|1[1]-1]{®)>®|1/0[1]1 7 | 2z 110]-2{0 0|0 |A)<B|O|0]]]|b 11012101 [+1[(A)<B)|o 0|0l fl [ 110|211 O 2|m=@|ol1]ol0 ALER = Z + NWVa NV 1{ol-211[1]-1]@™<@®|i|o]|l |0 =7+ p@V 111[1]o0jlolo|@=<®|c|ol]|0 1111 lol1|+1|l@a<@®]|o]oli | 111111102 ]A)>@®]|0|o|o]o0 111111 11|1]l®w=@®)]|0o|1]|0]0 i 00 00 0 10 10 10 o 1o 11\ T -ot 10 00 1 ol lo 00 —po b ek PP S D Y Rl &1 110 Lot o, 1 Lo
ECE 270 Introduction to Digital System Design Spring 2014 In-Class Homework for Module 4 — No. 3 Monday, April 14, 2014 In the BCD full adder illustrated below, the correction circuit adds 0110, to the “direct sum” (Z37,7,7,) under certain conditions to produce a valid BCD result. Derive the function, F(Z4737,7,7,), that is “1” when 0110, is to be added to the direct sum to produce a valid BCD result (S35,5:5), and is “0” otherwise. l | 1111 X3 X2 X1 X0 Y3 Y2 Y1 YO Cout 4-bit Adder Cin |« S3 S2 S1 S0 v v v L v Z4 73 Z2 7Z1 20 Correction Circuit Cout S3 S2 S1 SO T 0 4 1 8 : 200 [ 29 N [24 o "o [T 0 | T e 71 1 5 B9 71" [7 o1 o[t © | d 3 7 o |1 1y 70 19 z0 71 3 6 0 71 i3 | ol O % g} /% UL d ) zo 72’ 72 72’ 72 72 72’ VZZsZalil)= LA L5 2\ Z3+74
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ECE 270 Introduction to Digital System Design In-Class Homework for Module 4 — No. 2a Wednesday, April 16, 2014 Spring 2014 Given the “snapshot” of memory shown, calculate the result stored in memory along with the condition codes generated when each “shaded” region of machine code is executed. Opcode | Mnemonic | Description Opcode | Mnemonic | Description 0 0 0| HLT Stop execution |0 1 1 | AND addr | (A) <« (A)n(addr) 0 0 1|1LDA addr | (7)<« (addr) 1 0 0|SUB addr | (A) <« (A)-(addr) 0 1 0| STA addr | (addr) <« (2) 1 01 ADD addr| (A) <« (A)+(addr) INITIAL CONTENTS Location | Contents AFTER 1 BLOCK Location Contents 00000 | 001 01101 00001 | 011 01110 00010 | 010 01100 00011 | 001 01110 00100 | 100 01111| | CF = O 00101 | 010 01011 cr = 0 00101 010 01011 00110 | 001 01111 - 00110 | 001 01111 NE = 0 00111 |101 01110 NE = O 00111 | 101 01110 01000 | 010 01010 01000 | 010 01010 VE = 0 01001 | 000 00000 VE = 0 01001 | 000 00000 01010 01010 ZF = 0 01011 ZF = L 01011 01100 |0 OlL opib 01100 01101 {0111 1011 61t folf 01101 | 0111 1011 01110 } 1011 0110 L (011 011D 01110 1011 0110 01111 0110 1110 M‘“"T"‘””S’”m“ 01111 | o110 1110 001 AFTER 2™ BLOCK [ AFTER 3" BLOCK - ocation Contents Location Conftents 00000 | 001 01101 00000 [ 001 01101 00001 011 01110 00001 | 011 01110 00010 | 010 01100 00010 |010 01100 00011 | 001 01110 0 CF = 0 00100 | 100 01111 CF = _| 00101 [ 010 01011 NE = O e | NF - 00110 | 001 01111 , =B — 00111 | 101 01110} | yp - ! 1 i | ve = 0 01000 | 010 01010 01001 | 000 00000 01001 {000 00000 | zr = O 01010 {0015 otoo| | 28 = O 81812 e | [01011 o100 (oo : 4 ppto | 01100 011 0o gty 01100 } 0ol ODQOfifiiéifli :%ugwfl 01101 %151 01| O\\0 &n% 01101 | 011 1011 j—"" , | 01110 |1011 o110 * !0\ —— giiig 3211 0110 | Doolodp | 01111 |0i10 1330] |0 010 ° 0 1110 A
ECE 270 Given the “snapshot” of memory shown, calculate the result stored in memory along with Introduction to Digital System Design In-Class Homework for Module 4 — No. 2b Wednesday, April 16, 2014 Spring 2014 the condition codes generated when each “shaded” region of machine code is executed. Opcode | Mnemonic | Description Opcode | Mnemonic | Description 0 0 0 HLT Stop execution |0 1 1 | NGA (A) « (1) 0 0 1|LDA addr | (A)< (addr) 1 0 0|SUB addr | (A) <« (A)-(addr) 0 1 0| STA addr | (addr) <« (A) 1 0 1 |ADD addr | (A) <« (A)+(addr) INITIAL CONTENTS AFTER 1" BLOCK Location Contents Location Contents 00000 |001 01101 00001 | 011 00000 00010 | 010 01100 00011 | 001 01110 00011 | 001 01110 00100 100 01111 | CF = 0 00100 | 100 01111| | CF = _O_ 00101 | 010 01011 00101 | 010 01011 00110 [001 o1iil]| | NF =0 00110 |001 01111 | NF = | 00111 {101 01110 00111 | 101 01110 01000 | 010 01010]| | VF = O 01000 [010 oto010] | VF = O 01001 | 000 00000 2F = 0 01001 [ 000 00000 sr = O 01010 01010 T 01011 01011 01100 01100 || pp0 O]0] Ol 1ol 01101 | 0111 1011 01101 }o111 1011| —— 01110 |1011 0110 01110 [ 1011 0110 00D 0100 01111 | 0110 1110 01111 [ 0110 1110 | S d {;\;T\a po B0 { QE AFTER 2™ BLOCK AFTER 3™ BLOCK et Location Contents Location Contents 00000 | 001 01101 00000 | 001 01101 00001 {011 00000 00001 | 011 00000 00010 | 010 01100 00010 | 010 01100 | [cr - O 00011 | 001 01110 | oy = | — 00100 [ 100 01111 — Ng = O 00101 00111 | 101 01110| | yp = | 01000 | 010 01010 — 01001 | 000 00000 v = 0 01010 e 01010 | oo {0 bigo 81]0-11 gioo 1000 011 011D ;51;0529 01011 | 5100 gm;m 00 QQ@Q @m\@% | piio 111D Loy pool 01100 i@@@ @éi}é 01101 | 0111 1011 [— | 01101 [ 0111 1011 01110 {1011 0110 (31061600 01110 | 1011 0110 01111 [ 0110 1110 =t 01111 [ 0110 1110
ECE 270 Introduction to Digital System Design In-Class Homework for Module 4 — No. 4c¢ Wednesday, April 16, 2014 Spring 2014 Using the parts provided plus any additional logic gates you deem necessary, complete the BLOCK DIAGRAM for one bit (“i””) of the ALU defined as follows: AOCE | ALE | ALX | ALY | Function Performed CF | ZF | NF | VF 0 1 0 0 |aADD: [Q3.Q0]«[Q3..Q0)+[D3.DO} | &6 | & | & | & 0 1 0 1 |suB: [Q3.Q0]«[Q3.Q0]-[D3.D0] | ¢ | & | © | ¢ 0 1 1 0 |aND: [Q3..Q0] <« [Q3..Q0]N[D3.D0J| ¢ | & | § | e 0 1 1 1 |1pa: [Q3..Q0] «[D3..D0] o | $ | $ | o 1 0 d d |ouT: [D3.D0] « [Q3..Q0] ® ® ® ® 0 0 d d | (no operation — retain state) o | o | o | @ PR “$” indicates the flag is affected by the function performed, “®” indicates the flag is not affected | ! ALY =i Al A0 1, 2:1 mux Full Adder Cin 4“—C, F "Cout S ; G j Al A0 Q AL:\A —P i, 2:1mux —» D CLOCK Al A0 ALE—P i, 2:1 mux F
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ECE 270 Introduction to Digital System Design Spring 2014 In-Class Homework for Module 4 — No. 5 Monday, April 21, 2014 Simple Computer Functional Block Review Before class on April 21st, view the online video for Module 4-1. Complete the skeletal section that follows for your assigned functional block. Be prepared to present and discuss the completed skeletal section of your functional block and any ABEL code that may be associated with it. Cirele the functional block you have been assigned: Memory Program Counter (PC) Instruction Register (IR) Arithmetic Logic Unit (ALU) Instruction Decoder Microsequencer (IDMS) Address Bus 17
ECE 270 Memor Introduction to Digital System Design Spring 2014 o Tunction - a place to store the program, operands, and computation results e Modes of operation O Read - An address is placed on the address lines while CS and OE are asserted; the latch outputs for the selected location are output on the data lines Write - An address is placed on the address lines, data is placed on the data lines, then CS and WE are asserted; the latches of the selected location open, and the data is stored e RWM - read/write memory is given to memory arrays in which we can store and retrieve information at any time e RAM - random-access memories means that the time it takes to read or write a bit of memory is independent of the bit’s location in the RAM e Volatile memory — data that is lost if power is removed e Control inputs O O a chip select (CS) signal that serves as the overall enable for the memory chip an output enable (OE) signal that tells the memory chip to drive the data output lines with the contents of the memory location specified on its address lines a write enable (WE) signal that tells the memory chip to write the data supplied on its data input lines at the memory location specified on its address lines e Control signals O O O MSL: Memory SelLect MOE: Memory Output Enable MWE: Memory Write Enable e Other notable information
ECE 270 Introduction to Digital System Design Spring 2014 Pi'dgram Counter (PC) e Function - a way to keep track of which instruction is to be executed next. The , program counter (PC) is basically a binary “up” counter with tri-state outputs e Control signals o ARS: Asynchronous ReSet o PCC: Program Counter Count enable o POA: Program counter Output on Address bus tri-state buffer enable e PCin ABEL e Other notable information
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ECE 270 Introduction to Digital System Design Spring 2014 Instruction Register (IR) - e TFunction - a place to temporarily “stage” an instruction while it is being executed. The instruction register (IR) is basically an 8-bit data register, with tri-state outputs on the lower 5 bits. e Control signals o IRL: Instruction Register Load enable ' o IRA: Instruction Register Address field tri-state output enable e IR in ABEL e Other notable information o Note that the upper 3 bits (opcode field) are output directly to the instruction decoder and micro-sequencer
ECE 270 Introduction to Digital System Design Spring 2014 Arithmetic Logic Unit (ALU) o Function - a way to perform arithmetic and logic operations. ALU is a multi- function register that performs all the arithmetic and logical (Boolean) operations necessary to implement the instruction set. e Control signals o ALE: ALU Enable o ALX: ALU “X” function select o ALY: ALU “Y” function select o AOE: A register tri-state Output Enable e ALU in ABEL o Other notable information
ECE 270 Introduction to Digital System Design Spring 2014 Instruction Decoder and Microsequencer (IDMS) e Function - a way to coordinate and sequence the functions of the machine. The instruction decoder and microsequencer (IDMS) is a state machine that orchestrates the activity of all the other functional blocks. e There are two basic steps involved in “processing” each instruction of a program (called a micro-sequence): o fetching the instruction from memory (at the location pointed to by the PC), loading it into the IR, and incrementing the PC o executing the instruction staged in the IR based on the opcode field and the operand address field e The control signals that need to be asserted during the fetch cycle include: o POA: turn on PC output buffers o MSL: select memory o MOE: turn on memory output buffers o IRL: enable IR load o PCC: enable PC count e The control signals that need to be asserted during an execute cycle for the synchronous ALU functions (ADD, SUB, LDA, AND) are: o IRA: turn on operand address output buffers o MSL: select memory o MOE: turn on memory data output buffers o ALE: enable ALU operation o ALX, ALY: select ALU function e The control signals that need to be asserted during an execute cycle for STA are: o IRA: turn on operand address output buffers o MSL: select memory o MWE: enable memory write o AOE: turn on A register output buffers IDMS in ABEL e Other notable information
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ECE 270 Introduction to Digital System Design Spring 2014 In-Class Homework for Module 4 — No. 6 Wednesday, April 23, 2014 List the signals asserted on each cycle for the Simple Computer described on the Reference Sheet. Assume that the stack pointer points to the next available location. Decoded | Instruction . State Mnemonic Signals Asserted on Each Cycle S0 Fetch g/OA %j% P% g5]% {%Ef é EQJ %‘}flfi Jw’g ? st | o IRA MSL, )\/\ = ALE ALX,RSW 1 AR ALE, Aw,xag é““%fl RST s1 ADD I%ZA NSL V\OE; ALE, RST 51 SUB | IKA MSL @PMGE AUM% f, RST st | P ISPA, MSL, MWE, AOE, SPD, RST st | eoe |01 s2 PSH — s2 POP SPA") {I\/\SL’MOEj ALE?/E\L%} %;?T
ECE 270 Introduction to Digital System Design Spring 2014 Simple Computer Instruction Set: Opcode | Mnemonic | Description Opcode | Mnemonic | Description 0 0 0 | HLT Stop execution 10 0| ADD addr | (A) <« (A)+(addr) 0 0 1 | IDA addr | (A)<« (addr) 1 0 1 |8SUB addr | (A) <« (A)-(addr) 0 1 0| STA addr | (addr) < (2) 11 0| PSH Push (A) on to stack 0 1 1] ASR Arithmetic Shift Right |1 1 1 | POP Pop (A) off of stack Simple Computer ALU Function Table: AOE | ALE | ALX | ALY | Function CF | ZF | NF | VF 0 1 0 0 Add X | X1 X | X 0 1 0 1 Subtract X | X1 X | X 0 1 1 0 Load o | X | X | o 0 1 1 1 Arithmetic ShiftRight* | X | X | X | o 1 0 d d Output ® ° ° o 0 0 d d <none> ° ° ° e X —> flag affected, o — flag not affected *For Arithmetic Shift Right, CF = bit shifted out of accumulator Simple Computer Signal Names: ‘Name Description START | Asynchronous Machine Reset MSL Memory Select MOE Memory Output Tri-State Enable MWE Memory Write Enable PCC Program Counter Count Enable POA Program Counter Output on Address Bus Tri-State Enable PLA Program Counter Load from Address Bus Enable POD Program Counter Output on Data Bus Tri-State Enable PLD Program Counter Load from Data Bus Enable IRL Instruction Register Load Enable IRA Instruction Register Output on Address Bus Tri-State Enable AOE A-register Output on Data Bus Tri-State Enable ALE ALU Function Enable ALX ALU Function Select Line “X” ALY ALU Function Select Line “Y” SPI Stack Pointer Increment SPD Stack Pointer Decrement SPA Stack Pointer Output on Address Bus Tri-State Enable RST Synchronous State Counter Reset RUN Machine Run Enable 'Address Bus SIMPLE COMPUTER REFERENCE SHEET
ECE 270 Introduction to Digital System Design Spring 2014 In-Class Homework for Module 4 — No. 7 Monday, April 28, 2014 Show how the system control table for the JSR and RTS instructions would change for the Simple Computer in the notes if the alfernate stack convention (where SP points to next available location) were used. Use the minimum number of execute states possible for each instruction. Dec. | Instr. State | Mnem. MSL MOE MWE PCC POA IRL RA AOE ALE ALX ALY PLA POD PLD SPI SPD SPA RST I T | T} T | s1 | Jsr I H H H T S$1 RTS H s2 | JSR H H T s2 | RTs | H H H S3 JSR S3 RTS
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