ALU Lab

CEG 2136 Lab 3 - Arithmetic Logic Unit Fall 2023 University of Ottawa TAs Pulkit, Daksh, and Vrudant Saja Elkurtehi 300288667 Raveena Kumar 300321471 Experimented on: Oct 11 th & Oct 18 th & Nov 1 st 2023 Submitted on: Nov 5 th 2023

Theory Lab Problem The primary objective of this lab is to create an Arithmetic Logic Unit (ALU) by integrating various components like registers, 4-bit arithmetic and logic circuits, a 4-bit status register, and multiplexers. This lab holds significance as ALUs are essential in computer architecture and are employed in various digital systems, offering an opportunity to enhance our understanding of ALUs. A secondary goal is to refine our skills in designing logical circuits and utilizing the Altera DE2-115 board. Problem Discussion Problem Statement: The challenge is to construct an ALU through the sequential connection of a 4-bit register, 4-bit arithmetic circuit, 4-bit logic circuit, 4-bit status register, and multiplexers. This requires a strong grasp of Quartus software, familiarity with the Altera DE2-115 board, and a basic comprehension of ALU functionality. To build the ALU, it is necessary to incorporate all the aforementioned components, as well as a 1-bit logic circuit to form the 4-bit logic circuit, and a 1-bit full adder to construct the 4-bit arithmetic circuit. Additionally, basic logic gates such as AND, NOT, OR, NAND, NOR, and XOR gates will be employed in the design. Fig. 1 EU Datapath diagram In this depiction, you'll find the overall layout of the ALU, along with its core elements, such as registers and the Arithmetic unit. We're using this as our guide for crafting the ultimate logic diagram to be employed in Quartus. Our designed ALU has the task of executing 16 distinct micro operations as detailed in the accompanying table. 1

In this table, we delve into the prerequisites for our trusty 4-bit arithmetic unit while unveiling the inner workings of multiplexor inputs and their corresponding output goals. Fig. 2 1 bit arithmetic unit schematic This design for a 1-bit arithmetic unit was derived from table 2 above. Fig. 3 4 bit arithmetic unit schematic The 1 bit circuit designed in figure 2 was extended to support 4 bit inputs. 3

Table 3. Logical Micro-Operations (S3 = 1) S2 S1 S0 op1 op2 cy_in CL output 0 0 0 A B 0 CA <-0 0 0 1 A B 1 CA <- 1 0 1 0 A 0 0 CA <- A . B 0 1 1 A 0 1 CA <- A + B 1 0 0 A -B 0 CA <- A xor B 1 0 1 A -B 1 CA <- A . B’ 1 1 0 -A 0 0 CA <- A -1 1 1 1 -A 0 1 CA <- A +1 Similarly, this table outlines the multiplexor inputs for the logic circuit. Fig. 4 1-Bit logic circuit schematic Given the table above, this logic unit was derived for a 1 bit circuit. 4

Discussion of Used Components Hardware - Altera DE2-115 board PC (with Altera Quartus II running) USB blaster cable Software - Quartus II - And, Not, Xor, Nor, and Nand gates were all used for this lab. These were used to create the D-Flip flops that were used for the register, the full adder that was used for the arithmetic circuit, and the 4 bit state register. A multiplexer was also used at the end of the circuit which gave the final output. Discussion of Actual Solution Fig. 7 ALU Schematic The design above is the final schematic designed on the Quartus graphical editor. The selection inputs dictate the data flow of the two, four bit inputs: A and B. Selection input 3 (S3) dictates the use of the arithmetic/logic circuit while the three remaining select the operation to be done within that unit. The status indicator can display when an overflow occurs, when the output is negative, when there is a carry and when the output is zero. The remaining four bits are the result of the operation completed. The registers are used to store the data and are updated based on a clock pulse. The schematic above works as expected and produces the following simulation results. 6

Fig. 8 ALU simulation waveform Figure.9 validation of experimental results Discussion of Challenging Problems The most difficult aspect we faced in this lab was creating the ALU design in the Quartus software due to the extensive network of wires, numerous components, and input/output pins involved. Connecting all these elements demanded more effort than any other aspect of the lab work. Conclusion In the end, we can confidently state that all the components of this lab were completed successfully. We managed to design, compile, and thoroughly test every circuit, and our results were validated by the successful execution of our designs on the Altera board. The most significant challenge we encountered was related to errors in the ALU design. Given its intricate nature, we occasionally misplaced wires, leading to substantial time invested in identifying and rectifying these errors. Throughout this lab, we gained valuable insights into the constituent elements of an ALU and honed our proficiency in designing a comprehensive ALU. 7