COA_HW5

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COSC 2425: Computer Organization and Architecture Homework 5 (Chapter 5) Due: November 27 th , 2023, 11:59 PM Ques # Grade Q1 10 Q2 10 Q3 10 Q4 10 Total 40 Please use the solution sheet to submit your answers. 1. Submissions are only allowed in the format provided in the solution sheet. 2. The solution sheet is a word document (COA_HW5_Solution_Sheet.docx). 3. Download the solution sheet. The sheet has a table with question numbers. 4. Edit the word document by filling in your solution in the corresponding boxes in the table. 5. Points are allocated both for final answer and your work/formula. 6. Please show your work clearly and how you arrived at the solution.

Caches Question 1: An n-way set-associative cache consists of several sets, each of which consists of n blocks. Each block in the memory maps to a unique set in the cache given by the index field, and a block can be placed in any element of that set. Figure below shows an example of a direct mapped, 2-way set associative, 4-way set associative, and fully associative cache with 8 blocks. Consider a memory system that uses 32-bit memory addresses and a cache with a block size of 128 bytes. a. Assume a direct mapped cache with a tag field in the address of 20 bits. Determine the number of cache blocks, and the number of bits required for the byte offset. b. Assume a fully associative cache. Determine the number of bits required for the byte offset. c. Assume a four-way set-associative cache with a tag field size of 12 bits. Determine the number of cache sets, the number of cache blocks, and the number of bits required for the byte offset.

Question 2: Consider a direct-mapped cache design with a 64-bit address. The following bits of the address are used to access the cache. Tag Index Offset 63-14 13-6 5-0 a. What is the cache block size? b. How many blocks does the cache have? c. What is the ratio between the total bits required for such a cache implementation over the data storage bits? Note that the total bits include the tag and valid bits as well. Question 3: By convention, a cache is named according to the amount of data it contains (i.e., a 4 KiB cache can hold 4 KiB of data); however, caches also require SRAM to store metadata such as tags and valid bits. For this exercise, you will examine how a cache’s configuration affects the total amount of SRAM needed to implement it as well as the performance of the cache. For all parts, assume that the caches are byte addressable, that addresses are 64 bits and words are 32 bits. a. Calculate the total number of bits required to implement a 16 KiB cache with four-word blocks. b. Calculate the total number of bits required to implement a 64 KiB cache with 16-word blocks. c. How much bigger is the 64 KiB cache (implementation) than the 16 KiB cache (implementation). Question 4: Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The following table shows data for L1 caches attached to each of two processors, P1 and P2. L1 Size L1 Miss Rate L1 Hit Time P1 2KiB 15% 0.81 ns P2 4KiB 10% 0.86 ns a. Assuming the L1 hit time determines cycle times for P1 and P2, what are their clock rates? b. What is the Average Memory Access Time for P1 and P2 (in cycles)? c. Assuming a base CPI (Cycles Per Instruction) of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster? (When we say a “base CPI of 1.0”, we mean that instructions complete in one cycle, unless either the instruction access or the data access causes a cache miss.)

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