Compuetr Systems and Concepts Assignment-3

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Manoj Kumar Reddy Mule U01942405 MM99806N@pac.edu Assignment-3 4.6 How do data locality and instruction locality relate to spatial locality and temporal locality? Answer: Certainly! Let’s delve into the relationships between data locality , instruction locality , spatial locality , and temporal locality : 1. Data Locality and Spatial Locality : o Data Locality refers to the tendency of a program to access data elements (instructions or data) that are close in storage locations . o Spatial Locality specifically focuses on nearby instructions relative to the recently executed instruction. These nearby instructions have a high likelihood of being executed soon. o In other words, when a program accesses one data item, it is likely to access other data items stored close to it in memory. o Example: Accessing elements in an array where different (or just next) elements are accessed sequentially. 2. Instruction Locality and Temporal Locality : o Instruction Locality (also known as code locality ) pertains to the tendency of execution involving several memory locations. o Temporal Locality emphasizes that a recently executed instruction is likely to be executed again very soon. o When an instruction is executed, it is kept in cache memory so that it can be fetched easily without time-consuming searches. o Example: Repeatedly executing the same instructions within a short time span, such as in loops. S.No. Spatial Locality Temporal Locality 1. In Spatial Locality, nearby instructions to recently executed instruction are likely to be executed soon. In Temporal Locality, a recently executed instruction is likely to be executed again very soon. 2. It refers to the tendency of execution which involve several memory locations . It refers to the tendency of execution where memory location that have been used recently have a access. 3. It is also known as locality in space. It is also known as locality in time. 4. It only refers to data item which are closed together in memory. It repeatedly refers to same data in short time span. 5. Each time new data comes into execution. Each time same useful data comes into execution. 6. Example : Data elements accessed in array (where each time different (or just next) element is being accessing ). Example : Data elements accessed in loops (where same data elements are accessed multiple times).
Manoj Kumar Reddy Mule U01942405 MM99806N@pac.edu 4.7 . A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory but not in the cache, 60 ns are needed to load it into the cache, and then the reference is started again. If the word is not in main memory, 12 ns are required to fetch the word from the disk, followed by 60 ns to copy it to the cache, and then the reference is started again. The cache hit ratio is 0.9 and the main memory hit ratio is 0.6. What is the average time in nanoseconds required to access a referenced word on this system? Answer: Given the cache hit ratio (0.9) and the main memory hit ratio (0.6), we can calculate the average access time using these probabilities. Let's denote: Tc= Time for cache hit (20 ns) Tm= Time for cache miss with main memory hit (60 ns) Td= Time for cache miss with disk access (12 ns + 60 ns) Pc = Probability of a cache hit (0.9) Pm= Probability of a cache miss with main memory hit (0.1 * 0.6) Pd= Probability of a cache miss with disk access (0.1 * 0.4) Now, we can calculate the average access time: Average Access Time= Pc.Tc+ Pm.Tm+Pd.Td = (0.9 20)+(0.06 60)+(0.04 (12+60)) =(0.9 20)+(0.06 60)+(0.04 (12+60)) =(18)+(3.6)+(3.6+2.4) =18+3.6+6 =27.6 ns So, the average time required to access a referenced word on this system is 27.6 nanoseconds.
Manoj Kumar Reddy Mule U01942405 MM99806N@pac.edu 4.13 For the cache design of the preceding problem, suppose that increasing the line size from one word to four words results in a decrease of the read miss rate from 3.2% to 1.1%. For both the non-burst transfer and the burst transfer case, what is the average miss penalty, averaged over all reads, for the two different line sizes? Answer: Given: - Original miss rate (one-word line size): 3.2% - Miss rate with increased line size (four-word line size): 1.1% Let's denote: Por= Original miss rate (3.2%) Pnw = Miss rate with increased line size (1.1%) MPor = Miss penalty with one-word line size MPnw = Miss penalty with four-word line size The time it takes to read a block from memory to fill the cache (60 ns in this case) is the miss penalty for nonburst transfer. We can read four words in a single transfer for burst transfer if we increase the line size from one word to four words. Consequently, 60 ns/4 = 15 ns is the miss penalty for burst transfer with a four-word line size. Now, let's calculate the miss penalty for both line sizes: For the original one-word line size: MPor =60 ns For the increased four-word line size: MPnw =15 ns Now, we can calculate the average miss penalty for each line size, weighted by their respective miss rates: Average Miss Penaltyor = Por . MPor = (0.032) . (60)ns = 1.92 ns Average Miss Penaltynw = Pnw . MPnw = (0.011) . (60)ns = 1.92 ns Now, we need to average these over all reads. Since we have only two cases (one-word line size and four-word line size), we can directly average them: Average Miss Penalty = (Average Miss Penaltyor + Average Miss Penaltynw) / 2 = (1.92 ns + 0.165 ns)/2 = 2.085ns/2 =1.0425 ns
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Manoj Kumar Reddy Mule U01942405 MM99806N@pac.edu 4.14 Consider a two-level system with L1 instruction and data caches. For a given application, assume the following: instruction cache miss ratio =0.02 data cache miss ratio =0.04, and the fraction of instructions that are load/store= 0.36. The ideal value of CPI (cycles per instruction) without cache misses is 2.0. The penalty for a cache miss is 40 cycles. Calculate the CPI, taking misses into account. Answer: To calculate the CPI taking into account cache misses, we can use the given information and the formula: CPI= Ideal CPI+(Instruction Cache Miss Ratio × Penalty for Instruction Cache Miss) + (Data Cache Miss Ratio × Penalty for Data Cache Miss) Given: Ideal CPI without cache misses = 2.0 Penalty for a cache miss = 40 cycles Instruction cache miss ratio (ICMR) = 0.02 Data cache miss ratio (DCMR) = 0.04 Fraction of instructions that are load/store (FIS) = 0.36 First, let's calculate the penalties for instruction and data cache misses: Penalty for Instruction Cache Miss=40 cycles Penalty for Data Cache Miss=40 cycles Now, we can calculate the CPI: CPI=2.0+(ICMR × Penalty for Instruction Cache Miss)+(DCMR × Penalty for Data Cache Miss) =2.0 +(0.02×40)+(0.04×40) =2.0+0.8+1.6 =2.0+2.4 =4.4 So, the CPI taking misses into account is 4.4 cycles per instruction.
Manoj Kumar Reddy Mule U01942405 MM99806N@pac.edu References: https://github.com/AbderrhmanAbdellatif/ComputerOrganization/blob/ master/%5BThe%20Morgan%20Kaufmann%20Series%20in%20Computer %20Architecture%20and%20Design%5D%20David%20A.%20Patterson%2C %20John%20L.%20Hennessy%20-%20Computer%20Organization%20and %20Design_%20The%20Hardware%20Software%20Interface_%20ARM %20Edition%20(2016%2C%20Morgan%20Kaufmann).pdf google.com https://en.wikipedia.org/wiki/Locality_of_reference https://www.geeksforgeeks.org/difference-between-spatial-locality-and- temporal-locality/