POWER SYS. ANALYSIS+DESIGN
6th Edition
ISBN: 9780357700907
Author: Glover
Publisher: INTER CENG
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Figure 2
3) *** The circuit of Figure 3 is designed with W/L = 20/0.18, λ= 0, and ID = 0.25 mA.
(Optional- 20 points)
a) Compute the required gate bias voltage.
b) With such a gate voltage, how much can W/L be increased while M1 remains in
saturation? What is the maximum voltage gain that can be achieved as W/L
increases?
VDD = 1.8 V
RD 2k
- Vout
Vin M₁
Figure 3
1) Rs = 4kQ, R₁ = 850 kQ, R₂ = 350 kQ, and R₁ = 4 kQ. The transistor parameters are
VTP = -12 V, K'p = 40 µA / V², W/L = 80, and λ = 0.05 V-1. (50 Points)
a) Determine IDQ and VSDQ.
b) Find the small signal voltage gain. (Av)
c) Determine the small signal circuit transconductance gain. (Ag = io/vi)
d) Find the small signal output resistance.
VDD = 10 V
2';
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Figure 1
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