ELECTRICITY FOR TRADES
3rd Edition
ISBN: 9780078118630
Author: Petruzella
Publisher: RENT MCG
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Textbook Question
Chapter 5.1, Problem 4RQ
Explain how circuit breakers and fuses protect a circuit.
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Students have asked these similar questions
7. Consider the following feedback system with a proportional controller.
K
G(s)
The plant transfer function is given by
G(s) =
10
(s + 2)(s + 10)
You want the system to have a damping ratio of 0.3 for unit step response. What is the
value of K you need to choose to achieve the desired damping ratio? For that value of
K, find the steady-state error for ramp input and settling time for step input.
Hint: Sketch the root locus and find the point in the root locus that intersects with z =
0.3 line.
Create the PLC ladder logic diagram
for the logic gate circuit displayed in
Figure 7-35. The pilot light red (PLTR)
output section has three inputs: PBR,
PBG, and SW. Pushbutton red (PBR)
and pushbutton green (PBG) are inputs
to an XOR logic gate. The output of the
XOR logic gate and the inverted switch
SW) are inputs to a two-input AND
logic gate. These inputs generate the
pilot light red (PLTR) output.
The two-input AND logic gate output
is also fed into a two-input NAND logic
PBR
PBG
SW
TSW
PLTR
Figure 7-35. Logic gate circuit for Example 7-3.
PLTW
Goodheart-Willcox Publisher
gate. The temperature switch (TSW) is the other input to the NAND logic gate. The output generated from
the NAND logic gate is labeled pilot light white (PLTW).
Imaginary Axis (seconds)
1
6. Root locus for a closed-loop system with L(s) =
is shown below.
s(s+4)(s+6)
15
10-
0.89
0.95
0.988
0.988
-10
0.95
-15
-25
0.89
20
Root Locus
0.81
0.7
0.56
0.38
0.2
5
10
15
System: sys
Gain: 239
Pole: -0.00417 +4.89
Damping: 0.000854
Overshoot (%): 99.7
Frequency (rad/s): 4.89
System: sys
Gain: 16.9
Pole: -1.57
Damping: 1
Overshoot (%): 0
Frequency (rad/s): 1.57
0.81
0.7
0.56
0.38
0.2
-20
-15
-10
-5
5
10
Real Axis (seconds)
From the values shown in the figure, compute the following.
a) Range of K for which the closed-loop system is stable.
b) Range of K for which the closed-loop step response will not have any overshoot.
Note that when all poles are real, the step response has no overshoot.
c) Smallest possible peak time of the system. Note that peak time is the smallest
when wa is the largest for the dominant pole.
d) Smallest possible settling time of the system. Note that peak time is the smallest
when σ is the largest for the dominant pole.
Chapter 5 Solutions
ELECTRICITY FOR TRADES
Ch. 5.1 - Prob. 1RQCh. 5.1 - Polarity markings are shown on symbols...Ch. 5.1 - Compare the type of voltage produced by a solar...Ch. 5.1 - Explain how circuit breakers and fuses protect a...Ch. 5.1 - What are the two basic functions of a switch?Ch. 5.1 - Compare the operation of a normally open and...Ch. 5.1 - What type of circuit component is a light bulb...Ch. 5.1 - In general, what is the function of resistors...Ch. 5.1 - Two wires are shown on an electrical diagram...Ch. 5.1 - Give one advantage and one limitation of the...
Ch. 5.1 - Explain why schematic diagrams are easier to read.Ch. 5.1 - What is a wiring diagram intended to show?Ch. 5.1 - Prob. 13RQCh. 5.1 - The one-line diagram is often used with a power...Ch. 5.2 - What best describes a simple circuit?Ch. 5.2 - A lamp is to turn ON when either one or the other...Ch. 5.2 - What connection of two or more switches can be...Ch. 5.2 - Three 120-V, 40-W incandescent lamps are connected...Ch. 5.2 - Two 12-V, 10-W lamps are connected in parallel to...Ch. 5.2 - A control system calls for a light to come on when...Ch. 5.2 - One bulb in a 20-string series-connected holiday...Ch. 5.2 - Prob. 8RQCh. 5.2 - Prob. 9RQCh. 5.2 - Prob. 10RQ
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- For a band-rejection filter, the response drops below this half power point at two locations as visualised in Figure 7, we need to find these frequencies. Let's call the lower frequency-3dB point as fr and the higher frequency -3dB point fH. We can then find out the bandwidth as f=fHfL, as illustrated in Figure 7. 0dB Af -3 dB Figure 7. Band reject filter response diagram Considering your AC simulation frequency response and referring to Figure 7, measure the following from your AC simulation. 1% accuracy: (a) Upper-3db Frequency (fH) = Hz (b) Lower-3db Frequency (fL) = Hz (c) Bandwidth (Aƒ) = Hz (d) Quality Factor (Q) =arrow_forwardP 4.4-21 Determine the values of the node voltages V1, V2, and v3 for the circuit shown in Figure P 4.4-21. 29 ww 12 V +51 Aia ww 22. +21 ΖΩ www ΖΩ w +371 ①1 1 Aarrow_forward1. What is the theoretical attenuation of the output voltage at the resonant frequency? Answer to within 1%, or enter 0, or infinity (as “inf”) Attenuation =arrow_forward
- What is the settling time for your output signal (BRF_OUT)? For this question, We define the settling time as the period of time it has taken for the output to settle into a steady state - ie when your oscillation first decays (aka reduces) to less than approximately 1/20 (5%) of the initial value. (a) Settling time = 22 μs Your last answer was interpreted as follows: Incorrect answer. Check 22 222 What is the peak to peak output voltage (BRF_OUT pp) at the steady state condition? You may need to use the zoom function to perform this calculation. Select a time point that is two times the settling time you answered in the question above. Answer to within 10% accuracy. (a) BRF_OUT pp= mVpp As you may have noticed, the output voltage amplitude is a tiny fraction of the input voltage, i.e. it has been significantly attenuated. Calculate the attenuation (decibels = dB) in the output signal as compared to the input based on the formula given below. Answer to within 1% accuracy.…arrow_forwardmy previous answers for a,b,d were wrong a = 1050 b = 950 d=9.99 c was the only correct value i got previously c = 100hz is correctarrow_forwardV₁(t) ww ZRI ZLI ZL2 ZTH Zci VTH Zc21 Figure 8. Circuit diagram showing calculation approach for VTH and Z TH we want to create a blackbox for the red region, we want to use the same input signal conditions as previously the design of your interference ector circuit: Sine wave with a 1 Vpp, with a frequency of 100 kHz (interference) Square wave with 2.4Vpp, with a frequency of 10 kHz (signal) member an AC Thevenin equivalent is only valid at one frequency. We have chosen to calculate the Thevenin equivalent circuit (and therefore the ackbox) at the interference frequency (i.e. 100 kHz), and the signal frequency (i.e. 10 kHz) as these are the key frequencies to analyse. Your boss is assured you that the waveform converter module has been pre-optimised to the DAB Receiver if you use the recommended circuit topology.arrow_forward
- Vs(t) + v(t) + vi(t) ZR ZL Figure 1: Second order RLC circuit Zc + ve(t) You are requested to design the circuit shown in Figure 1. The circuit is assumed to be operating at its resonant frequency when it is fed by a sinusoidal voltage source Vs (t) = 2sin(le6t). To help design your circuit you have been given the value of inductive reactance ZL = j1000. Assume that the amplitude of the current at resonance is Is (t) = 2 mA. Based on this information, answer the following to help design your circuit. Use cartesian notation for your answers, where required.arrow_forwardWhat is the attenuation at the resonant frequency? You should use the LTSpice cursors for your measurement. Answer to within 1% accuracy, or enter 0, or infinity (as "inf") (a) Attenuation (dB) = dB Check You may have noticed that it was significantly easier to use frequency-domain "AC" simulation to measure the attenuation, compared to the steps we performed in the last few questions. (i.e. via a time-domain "transient" simulation). AC analysis allows us to observe and quantify large scale positive or negative changes in a signal of interest across a wide range of different frequencies. From the response you will notice that only frequencies that are relatively close to 100 kHz have been attenuated. This is the result of the Band-reject filter you have designed, and shows the 'rejection' (aka attenuation) of any frequencies that lie in a given band. The obvious follow-up question is how do we define this band? We use a quantity known as the bandwidth. A commonly used measurement for…arrow_forwardV₁(t) ww ZRI ZLI ZL2 ZTH Zci VTH Zc21 Figure 8. Circuit diagram showing calculation approach for VTH and Z TH we want to create a blackbox for the red region, we want to use the same input signal conditions as previously the design of your interference ector circuit: Sine wave with a 1 Vpp, with a frequency of 100 kHz (interference) Square wave with 2.4Vpp, with a frequency of 10 kHz (signal) member an AC Thevenin equivalent is only valid at one frequency. We have chosen to calculate the Thevenin equivalent circuit (and therefore the ackbox) at the interference frequency (i.e. 100 kHz), and the signal frequency (i.e. 10 kHz) as these are the key frequencies to analyse. Your boss is assured you that the waveform converter module has been pre-optimised to the DAB Receiver if you use the recommended circuit topology.arrow_forward
- Vs(t) + v(t) + vi(t) ZR ZL Figure 1: Second order RLC circuit Zc + ve(t) You are requested to design the circuit shown in Figure 1. The circuit is assumed to be operating at its resonant frequency when it is fed by a sinusoidal voltage source Vs (t) = 2sin(le6t). To help design your circuit you have been given the value of inductive reactance ZL = j1000. Assume that the amplitude of the current at resonance is Is (t) = 2 mA. Based on this information, answer the following to help design your circuit. Use cartesian notation for your answers, where required.arrow_forwardFor a band-rejection filter, the response drops below this half power point at two locations as visualised in Figure 7, we need to find these frequencies. Let's call the lower frequency-3dB point as fr and the higher frequency -3dB point fH. We can then find out the bandwidth as f=fHfL, as illustrated in Figure 7. 0dB Af -3 dB Figure 7. Band reject filter response diagram Considering your AC simulation frequency response and referring to Figure 7, measure the following from your AC simulation. 1% accuracy: (a) Upper-3db Frequency (fH) = Hz (b) Lower-3db Frequency (fL) = Hz (c) Bandwidth (Aƒ) = Hz (d) Quality Factor (Q) =arrow_forwardV₁(t) ww ZRI ZLI Z12 Zci Zcz Figure 4. Notch filter circuit topology ши Consider the second order resonant circuit shown in Figure 4. Impedances ZLIZ C1. ZL2. Z c2 combine together forming a two-stage "band- reject" filter, so called because it rejects a "band" (aka range) of frequencies. This circuit topology is also commonly referred to as a "band-stop" filter or "notch" filter. The output of the DAB receiver block has been approximated via Thevenin's theorem for you as a voltage source Vs (t) and associated series impedance Z RI To succeed in our goal, we are going to use an iterative design approach. First we will design the interference rejector, and then repeat the process, using the output of the interference rejector to check the provided waveform converter works as intended.arrow_forward
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