a. Explanation for the given code: In the give code, “A” and “B” are the arrays of pointer to structures. Every pointer is four bytes long. The programmers are interested in the value of fields at an offset of 12 bytes from the beginning of the structure. The C source program might look something like S := A [k] → f + B[k] → f;

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Answer 1

Expert Solution & Answer

Chapter 5, Problem 16E

Explanation of Solution

a.

Explanation for the given code:

In the give code, “A” and “B” are the arrays of pointer to structures.

Every pointer is four bytes long.

The programmers are interested in the value of fields at an offset of 12 bytes from the beginning of the structure.

The C source program might look something like S := A [k] → f + B[k] → f;

Explanation of Solution

b.

Identifying flow dependences:

There are flow dependences from

Instruction 1 to instruction 4 (r1)

Instruction 2 to instruction 5 (r4)

Instruction 3 to instruction 8 (r6)

Instruction 4 to instruction 5 (r2)

Instruction 4 to instruction 8 (r2)

Instruction 5 to instruction 6 (r3)

Instruction 6 to instruction 7 (r3)

Instruction 7 to instruction 11 (r5)

Instruction 8 to instruction 9 (r3)

Instruction 9 to instruction 10 (r3)

Instruction 10 to instruction 11 (r7)

Instruction 11 to instruction 12 (r3)

Identifying anti-dependences:

There are anti-dependences from instruction 6 to 8, 9, and 11;

Instruction 7 to 8, 9, and 11;

Instruction 9 to 11; and

Instruction 10 to 11.

All of them are carried by “r3” register.

Identifying output dependences:

There are output dependences from instruction 5 to 6, 8, 9, and 11;

Instruction 6 to 8, 9, and 11;

Instruction 8 to 9 and 11; and

Instruction 9 to 11.

Again, all are carried by “r3” register.

Explanation of Solution

c.

Scheduling the code to reduce the load delay on a single-pipeline, in-order processor:

There are 3 load delays to worry about, after the instructions 6, 9, and 10.

The best way is to move an instruction down into the delay slot of instruction 6.

Modified code is as follows:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B −−−filled this slot7. r5 := (r3 + 12)8. r3 := r6 + r2 9. r3 := r3 −−−still a delay after this load10. r7 = *(r3 + 12) −−−and this one11. r3 := r5 + r712. S := r3

There will still be delays after instruction 9 and 10.

Explanation of Solution

d.

Justification:

“Yes”, if the programmer introduce a new register name (r8) for the reuse of “r3” at instruction 8 then the programmer can move the second load downward, where it becomes instruction 9:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B 7. r8 := r6+r18. r8 := r8 9. r5 := (r3+12) −−−filled this slot10. r7 = (r8 + 12) −−−still a delay after this load11. r3 := r5 + r712. S := r3

Without a longer window to consider, there is still no way to delete the delay after instruction 10.

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Whentheuserenters!!,themostrecentcommandinthehistoryisexecuted.In the example above, if the user entered the command: Osh> !! The ‘ls -l’ command should be executed and echoed on user’s screen. The command should also be placed in the history buffer as the next command. Whentheuserentersasingle!followedbyanintegerN,theNthcommandin the history is executed. In the example above, if the user entered the command: Osh> ! 3 The ‘ps’ command should be executed and echoed on the user’s screen. The command should also be placed in the history buffer as the next command. Error handling: The program should also manage basic error handling. For example, if there are no commands in the history, entering !! should result in a message “No commands in history.” Also, if there is no command corresponding to the number entered with the single !, the program should output "No such command in history."

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Answer 2

Expert Solution & Answer

Chapter 5, Problem 16E

Explanation of Solution

a.

Explanation for the given code:

In the give code, “A” and “B” are the arrays of pointer to structures.

Every pointer is four bytes long.

The programmers are interested in the value of fields at an offset of 12 bytes from the beginning of the structure.

The C source program might look something like S := A [k] → f + B[k] → f;

Explanation of Solution

b.

Identifying flow dependences:

There are flow dependences from

Instruction 1 to instruction 4 (r1)

Instruction 2 to instruction 5 (r4)

Instruction 3 to instruction 8 (r6)

Instruction 4 to instruction 5 (r2)

Instruction 4 to instruction 8 (r2)

Instruction 5 to instruction 6 (r3)

Instruction 6 to instruction 7 (r3)

Instruction 7 to instruction 11 (r5)

Instruction 8 to instruction 9 (r3)

Instruction 9 to instruction 10 (r3)

Instruction 10 to instruction 11 (r7)

Instruction 11 to instruction 12 (r3)

Identifying anti-dependences:

There are anti-dependences from instruction 6 to 8, 9, and 11;

Instruction 7 to 8, 9, and 11;

Instruction 9 to 11; and

Instruction 10 to 11.

All of them are carried by “r3” register.

Identifying output dependences:

There are output dependences from instruction 5 to 6, 8, 9, and 11;

Instruction 6 to 8, 9, and 11;

Instruction 8 to 9 and 11; and

Instruction 9 to 11.

Again, all are carried by “r3” register.

Explanation of Solution

c.

Scheduling the code to reduce the load delay on a single-pipeline, in-order processor:

There are 3 load delays to worry about, after the instructions 6, 9, and 10.

The best way is to move an instruction down into the delay slot of instruction 6.

Modified code is as follows:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B −−−filled this slot7. r5 := (r3 + 12)8. r3 := r6 + r2 9. r3 := r3 −−−still a delay after this load10. r7 = *(r3 + 12) −−−and this one11. r3 := r5 + r712. S := r3

There will still be delays after instruction 9 and 10.

Explanation of Solution

d.

Justification:

“Yes”, if the programmer introduce a new register name (r8) for the reuse of “r3” at instruction 8 then the programmer can move the second load downward, where it becomes instruction 9:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B 7. r8 := r6+r18. r8 := r8 9. r5 := (r3+12) −−−filled this slot10. r7 = (r8 + 12) −−−still a delay after this load11. r3 := r5 + r712. S := r3

Without a longer window to consider, there is still no way to delete the delay after instruction 10.

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Answer 3

Expert Solution & Answer

Chapter 5, Problem 16E

Explanation of Solution

a.

Explanation for the given code:

In the give code, “A” and “B” are the arrays of pointer to structures.

Every pointer is four bytes long.

The programmers are interested in the value of fields at an offset of 12 bytes from the beginning of the structure.

The C source program might look something like S := A [k] → f + B[k] → f;

Explanation of Solution

b.

Identifying flow dependences:

There are flow dependences from

Instruction 1 to instruction 4 (r1)

Instruction 2 to instruction 5 (r4)

Instruction 3 to instruction 8 (r6)

Instruction 4 to instruction 5 (r2)

Instruction 4 to instruction 8 (r2)

Instruction 5 to instruction 6 (r3)

Instruction 6 to instruction 7 (r3)

Instruction 7 to instruction 11 (r5)

Instruction 8 to instruction 9 (r3)

Instruction 9 to instruction 10 (r3)

Instruction 10 to instruction 11 (r7)

Instruction 11 to instruction 12 (r3)

Identifying anti-dependences:

There are anti-dependences from instruction 6 to 8, 9, and 11;

Instruction 7 to 8, 9, and 11;

Instruction 9 to 11; and

Instruction 10 to 11.

All of them are carried by “r3” register.

Identifying output dependences:

There are output dependences from instruction 5 to 6, 8, 9, and 11;

Instruction 6 to 8, 9, and 11;

Instruction 8 to 9 and 11; and

Instruction 9 to 11.

Again, all are carried by “r3” register.

Explanation of Solution

c.

Scheduling the code to reduce the load delay on a single-pipeline, in-order processor:

There are 3 load delays to worry about, after the instructions 6, 9, and 10.

The best way is to move an instruction down into the delay slot of instruction 6.

Modified code is as follows:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B −−−filled this slot7. r5 := (r3 + 12)8. r3 := r6 + r2 9. r3 := r3 −−−still a delay after this load10. r7 = *(r3 + 12) −−−and this one11. r3 := r5 + r712. S := r3

There will still be delays after instruction 9 and 10.

Explanation of Solution

d.

Justification:

“Yes”, if the programmer introduce a new register name (r8) for the reuse of “r3” at instruction 8 then the programmer can move the second load downward, where it becomes instruction 9:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B 7. r8 := r6+r18. r8 := r8 9. r5 := (r3+12) −−−filled this slot10. r7 = (r8 + 12) −−−still a delay after this load11. r3 := r5 + r712. S := r3

Without a longer window to consider, there is still no way to delete the delay after instruction 10.

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Answer 4

Expert Solution & Answer

Chapter 5, Problem 16E

Explanation of Solution

a.

Explanation for the given code:

In the give code, “A” and “B” are the arrays of pointer to structures.

Every pointer is four bytes long.

The programmers are interested in the value of fields at an offset of 12 bytes from the beginning of the structure.

The C source program might look something like S := A [k] → f + B[k] → f;

Explanation of Solution

b.

Identifying flow dependences:

There are flow dependences from

Instruction 1 to instruction 4 (r1)

Instruction 2 to instruction 5 (r4)

Instruction 3 to instruction 8 (r6)

Instruction 4 to instruction 5 (r2)

Instruction 4 to instruction 8 (r2)

Instruction 5 to instruction 6 (r3)

Instruction 6 to instruction 7 (r3)

Instruction 7 to instruction 11 (r5)

Instruction 8 to instruction 9 (r3)

Instruction 9 to instruction 10 (r3)

Instruction 10 to instruction 11 (r7)

Instruction 11 to instruction 12 (r3)

Identifying anti-dependences:

There are anti-dependences from instruction 6 to 8, 9, and 11;

Instruction 7 to 8, 9, and 11;

Instruction 9 to 11; and

Instruction 10 to 11.

All of them are carried by “r3” register.

Identifying output dependences:

There are output dependences from instruction 5 to 6, 8, 9, and 11;

Instruction 6 to 8, 9, and 11;

Instruction 8 to 9 and 11; and

Instruction 9 to 11.

Again, all are carried by “r3” register.

Explanation of Solution

c.

Scheduling the code to reduce the load delay on a single-pipeline, in-order processor:

There are 3 load delays to worry about, after the instructions 6, 9, and 10.

The best way is to move an instruction down into the delay slot of instruction 6.

Modified code is as follows:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B −−−filled this slot7. r5 := (r3 + 12)8. r3 := r6 + r2 9. r3 := r3 −−−still a delay after this load10. r7 = *(r3 + 12) −−−and this one11. r3 := r5 + r712. S := r3

There will still be delays after instruction 9 and 10.

Explanation of Solution

d.

Justification:

“Yes”, if the programmer introduce a new register name (r8) for the reuse of “r3” at instruction 8 then the programmer can move the second load downward, where it becomes instruction 9:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B 7. r8 := r6+r18. r8 := r8 9. r5 := (r3+12) −−−filled this slot10. r7 = (r8 + 12) −−−still a delay after this load11. r3 := r5 + r712. S := r3

Without a longer window to consider, there is still no way to delete the delay after instruction 10.

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Answer 5

Expert Solution & Answer

Answer 6

Expert Solution & Answer

Answer 7

Chapter 5, Problem 16E

Explanation of Solution

a.

Explanation for the given code:

In the give code, “A” and “B” are the arrays of pointer to structures.

Every pointer is four bytes long.

The programmers are interested in the value of fields at an offset of 12 bytes from the beginning of the structure.

The C source program might look something like S := A [k] → f + B[k] → f;

Explanation of Solution

b.

Identifying flow dependences:

There are flow dependences from

Instruction 1 to instruction 4 (r1)

Instruction 2 to instruction 5 (r4)

Instruction 3 to instruction 8 (r6)

Instruction 4 to instruction 5 (r2)

Instruction 4 to instruction 8 (r2)

Instruction 5 to instruction 6 (r3)

Instruction 6 to instruction 7 (r3)

Instruction 7 to instruction 11 (r5)

Instruction 8 to instruction 9 (r3)

Instruction 9 to instruction 10 (r3)

Instruction 10 to instruction 11 (r7)

Instruction 11 to instruction 12 (r3)

Identifying anti-dependences:

There are anti-dependences from instruction 6 to 8, 9, and 11;

Instruction 7 to 8, 9, and 11;

Instruction 9 to 11; and

Instruction 10 to 11.

All of them are carried by “r3” register.

Identifying output dependences:

There are output dependences from instruction 5 to 6, 8, 9, and 11;

Instruction 6 to 8, 9, and 11;

Instruction 8 to 9 and 11; and

Instruction 9 to 11.

Again, all are carried by “r3” register.

Explanation of Solution

c.

Scheduling the code to reduce the load delay on a single-pipeline, in-order processor:

There are 3 load delays to worry about, after the instructions 6, 9, and 10.

The best way is to move an instruction down into the delay slot of instruction 6.

Modified code is as follows:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B −−−filled this slot7. r5 := (r3 + 12)8. r3 := r6 + r2 9. r3 := r3 −−−still a delay after this load10. r7 = *(r3 + 12) −−−and this one11. r3 := r5 + r712. S := r3

There will still be delays after instruction 9 and 10.

Explanation of Solution

d.

Justification:

“Yes”, if the programmer introduce a new register name (r8) for the reuse of “r3” at instruction 8 then the programmer can move the second load downward, where it becomes instruction 9:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B 7. r8 := r6+r18. r8 := r8 9. r5 := (r3+12) −−−filled this slot10. r7 = (r8 + 12) −−−still a delay after this load11. r3 := r5 + r712. S := r3

Without a longer window to consider, there is still no way to delete the delay after instruction 10.

Answer 8

Chapter 5, Problem 16E

Explanation of Solution

a.

Explanation for the given code:

In the give code, “A” and “B” are the arrays of pointer to structures.

Every pointer is four bytes long.

The programmers are interested in the value of fields at an offset of 12 bytes from the beginning of the structure.

The C source program might look something like S := A [k] → f + B[k] → f;

Answer 9

Chapter 5, Problem 16E

Explanation of Solution

a.

Explanation for the given code:

In the give code, “A” and “B” are the arrays of pointer to structures.

Every pointer is four bytes long.

The programmers are interested in the value of fields at an offset of 12 bytes from the beginning of the structure.

The C source program might look something like S := A [k] → f + B[k] → f;

Answer 10

Explanation of Solution

b.

Identifying flow dependences:

There are flow dependences from

Instruction 1 to instruction 4 (r1)

Instruction 2 to instruction 5 (r4)

Instruction 3 to instruction 8 (r6)

Instruction 4 to instruction 5 (r2)

Instruction 4 to instruction 8 (r2)

Instruction 5 to instruction 6 (r3)

Instruction 6 to instruction 7 (r3)

Instruction 7 to instruction 11 (r5)

Instruction 8 to instruction 9 (r3)

Instruction 9 to instruction 10 (r3)

Instruction 10 to instruction 11 (r7)

Instruction 11 to instruction 12 (r3)

Identifying anti-dependences:

There are anti-dependences from instruction 6 to 8, 9, and 11;

Instruction 7 to 8, 9, and 11;

Instruction 9 to 11; and

Instruction 10 to 11.

All of them are carried by “r3” register.

Identifying output dependences:

There are output dependences from instruction 5 to 6, 8, 9, and 11;

Instruction 6 to 8, 9, and 11;

Instruction 8 to 9 and 11; and

Instruction 9 to 11.

Again, all are carried by “r3” register.

Answer 11

Explanation of Solution

b.

Identifying flow dependences:

There are flow dependences from

Instruction 1 to instruction 4 (r1)

Instruction 2 to instruction 5 (r4)

Instruction 3 to instruction 8 (r6)

Instruction 4 to instruction 5 (r2)

Instruction 4 to instruction 8 (r2)

Instruction 5 to instruction 6 (r3)

Instruction 6 to instruction 7 (r3)

Instruction 7 to instruction 11 (r5)

Instruction 8 to instruction 9 (r3)

Instruction 9 to instruction 10 (r3)

Instruction 10 to instruction 11 (r7)

Instruction 11 to instruction 12 (r3)

Identifying anti-dependences:

There are anti-dependences from instruction 6 to 8, 9, and 11;

Instruction 7 to 8, 9, and 11;

Instruction 9 to 11; and

Instruction 10 to 11.

All of them are carried by “r3” register.

Identifying output dependences:

There are output dependences from instruction 5 to 6, 8, 9, and 11;

Instruction 6 to 8, 9, and 11;

Instruction 8 to 9 and 11; and

Instruction 9 to 11.

Again, all are carried by “r3” register.

Answer 12

Explanation of Solution

c.

Scheduling the code to reduce the load delay on a single-pipeline, in-order processor:

There are 3 load delays to worry about, after the instructions 6, 9, and 10.

The best way is to move an instruction down into the delay slot of instruction 6.

Modified code is as follows:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B −−−filled this slot7. r5 := (r3 + 12)8. r3 := r6 + r2 9. r3 := r3 −−−still a delay after this load10. r7 = *(r3 + 12) −−−and this one11. r3 := r5 + r712. S := r3

There will still be delays after instruction 9 and 10.

Answer 13

Explanation of Solution

c.

Scheduling the code to reduce the load delay on a single-pipeline, in-order processor:

There are 3 load delays to worry about, after the instructions 6, 9, and 10.

The best way is to move an instruction down into the delay slot of instruction 6.

Modified code is as follows:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B −−−filled this slot7. r5 := (r3 + 12)8. r3 := r6 + r2 9. r3 := r3 −−−still a delay after this load10. r7 = *(r3 + 12) −−−and this one11. r3 := r5 + r712. S := r3

There will still be delays after instruction 9 and 10.

Answer 14

Explanation of Solution

d.

Justification:

“Yes”, if the programmer introduce a new register name (r8) for the reuse of “r3” at instruction 8 then the programmer can move the second load downward, where it becomes instruction 9:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B 7. r8 := r6+r18. r8 := r8 9. r5 := (r3+12) −−−filled this slot10. r7 = (r8 + 12) −−−still a delay after this load11. r3 := r5 + r712. S := r3

Without a longer window to consider, there is still no way to delete the delay after instruction 10.

Answer 15

Explanation of Solution

d.

Justification:

“Yes”, if the programmer introduce a new register name (r8) for the reuse of “r3” at instruction 8 then the programmer can move the second load downward, where it becomes instruction 9:

1. r1 := l2. r4 := &A3. r2 := r1 × 44. r3 := r4 + r25. r3 := r36. r6 := &B 7. r8 := r6+r18. r8 := r8 9. r5 := (r3+12) −−−filled this slot10. r7 = (r8 + 12) −−−still a delay after this load11. r3 := r5 + r712. S := r3

Without a longer window to consider, there is still no way to delete the delay after instruction 10.

Answer 16

Ch. 5.2 - Prob. 1CYU Ch. 5.2 - Prob. 2CYU Ch. 5.2 - Prob. 3CYU Ch. 5.2 - Prob. 4CYU Ch. 5.2 - Prob. 5CYU Ch. 5.2 - Prob. 6CYU Ch. 5.3 - Prob. 7CYU Ch. 5.3 - Prob. 8CYU Ch. 5.3 - Prob. 9CYU Ch. 5.3 - Prob. 10CYU

Explanation of Solution

Explanation of Solution

Explanation of Solution

Explanation of Solution

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Chapter 5 Solutions