Chapter 4, Problem 63E

Program Plan Intro

The RTN for “StoreI” instruction:

RTN is the register transfer notation which is used to represents the behavior of micro operations with the use of symbols. The “StoreI” instruction used to store the particular value in register. The register transfer notation (RTN) used to describe the micro operations of the instruction.

The RTN for “StoreI” as per given instruction:

$\begin{array}{l}\text{MAR}\leftarrow \text{PC}\\ \text{IR}\leftarrow \text{M[MAR]}\\ \text{PC}\leftarrow \text{PC+1}\\ \text{MAR}\leftarrow \text{IR[11-0]}\end{array}$

$\begin{array}{l}\text{MBR}\leftarrow \text{M[MAR]}\\ \text{MAR}\leftarrow \text{MBR}\\ \text{PC }\leftarrow \text{MBR}\\ \text{M[MAR]}\leftarrow \text{MBR}\\ \text{MBR}\leftarrow \text{AC}\end{array}$

Where,

• Memory Address Register (MAR)
• Memory Buffer Register (MBR)
• Program counter(PC)
• Instruction register(IR)
• Accumulator register (AC)

Explanation of Solution

Control signals for given “StoreI” instruction:

The data path control signals for each register as given below:

Register	Memory	MAR	PC	MBR	AC	IN	Out	IR
Signals	000	001	010	011	100	101	110	111
P2 P1 P0 (Read) P5 P4 P3(Write)

The control signals are varying based on read and write operations. The register values may vary in this. The RTN for “StoreI” instruction with its signals is as follows:

$\begin{array}{l}{\text{P}}_{\text{1}}{\text{ P}}_{\text{3}}{\text{ T}}_{\text{0}}\text{:MAR}\leftarrow \text{PC}\\ {\text{P}}_5{\text{ P}}_4{\text{ P}}_{\text{3}}{\text{ P}}_0{\text{ M}}_{\text{R}}{\text{T}}_{\text{1}}\text{:IR}\leftarrow \text{M[MAR]}\\ {\text{A}}_{\text{0}}{\text{ P}}_4{\text{ P}}_1{\text{ T}}_{\text{2}}\text{:PC}\leftarrow \text{PC+1}\\ {\text{P}}_{\text{3}}{\text{ P}}_2{\text{ P}}_1{\text{ P}}_0{\text{ T}}_3:\text{MAR}\leftarrow \text{IR[11-0]}\end{array}$

$\begin{array}{l}{\text{P}}_4{\text{ P}}_{\text{3}}{\text{ M}}_{\text{R}}{\text{T}}_4:\text{MBR}\leftarrow \text{M[MAR]}\\ {\text{P}}_4{\text{ P}}_{\text{3}}{\text{ P}}_2{\text{ T}}_5:\text{MAR}\leftarrow \text{MBR}\\ {\text{P}}_{\text{1}}{\text{ P}}_{\text{3}}{\text{ P}}_2{\text{ T}}_6:\text{MBR}\leftarrow \text{ AC}\\ {\text{P}}_{\text{1}}{\text{ P}}_0{\text{ M}}_{\text{W}}{\text{ T}}_7:\text{M[MAR]}\leftarrow \text{ MBR}\\ {\text{C}}_{\text{r}}{\text{ P}}_{\text{1}}{\text{ P}}_0{\text{ P}}_4{\text{ T}}_8{\text{ L}}_{\text{ALT}}\text{: PC}\leftarrow \text{ MBR[Reset the clock cycle counter]}\end{array}$

Here,

• “M_R” is memory read that enables the control line at time “T₁” and “T₂”.
• “L_ALT” is loading the values from the data wires inn registers like MBR, MAR, IR, and AC at time “T₁” and “T₂”.
• At time “T₀” all other signals except “P₁”, “P₃”, and “T₀” are low.  The signal “P₁” allows reading from PC and “P₃” writing to MAR.
• At time “T₁” all other signals except “P₃”, “P₄”, and “T₁” are low.  Repeat the process for the rest of clock times.
• The last instruction occurs at “T5” when the timing signals are reset to 0.

The control signals contain “1” for each instruction step with “JumpI” instruction is as follows:

Step	RTN	Time	P5	P4	P3	P2	P1	P0	CR	IncrPC	MR	MW	LALT
Fetch	MAR←PC	T0	0	0	1	0	1	0	0	0	0	0	0
	IR←M[MAR]	T1	1	1	1	0	0	1	0	0	1	0	1
Decode IR[15-12]	PC←PC+1	T2	0	1	0	0	1	0	0	1	0	0	0
Get operand	MAR←IR[11-0]	T3	0	0	1	1	1	1	0	0	0	0	0
Execute	MBR←M[MAR]	T4	0	1	1	0	0	0	0	0	1	0	1
	MAR←MBR	T5	0	0	1	0	1	1	0	0	0	0	0
	MBR←AC	T6	0	1	1	1	0	0	0	0	0	0	1
	M[MAR]←MBR	T7	0	0	0	0	1	1	0	0	0	1	0
	PC←MBR	T8	0	1	0	0	1	1	1	0	0	0	1