EBK ELECTRICAL WIRING RESIDENTIAL
EBK ELECTRICAL WIRING RESIDENTIAL
19th Edition
ISBN: 9781337516549
Author: Simmons
Publisher: CENGAGE LEARNING - CONSIGNMENT
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Chapter 2.1, Problem 1R

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4. a. Determine VDs for VGS = 0 V and ID = 6 mA using the characteristics of Fig. 6.11. b. Using the results of part (a), calculate the resistance of the JFET for the region ID = 0 to 6 mA for VGS = 0 V. c. Determine VDs for VGS = -1 V and ID = 3 mA. d. Using the results of part (c), calculate the resistance of the JFET for the region ID = 0 to 3 mA for VGS = -1 V. e. Determine VDs for VGS = -2 V and ID = 1.5 mA. f. Using the results of part (e), calculate the resistance of the JFET for the region ID = 0 to 1.5 mA for VGS = -2 V. g. Defining the result of part (b) as ro, determine the resistance for VGS = -1 V using Eq. (6.1) and compare with the results of part (d). h. Repeat part (g) for VGS = -2 V using the same equation, and compare the results with part (f). i. Based on the results of parts (g) and (h), does Eq. (6.1) appear to be a valid approximation?
A. Using D flip-flops, design a logic circuit for the finite-state machine described by the state assigned table in Fig. 1. Present Next State State Output x=0 x=1 Y2Y1 Y2Y1 YY Z 00 00 01 0 01 10 11 888 00 10 0 00 10 1 00 10 1 Fig. 1

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EBK ELECTRICAL WIRING RESIDENTIAL

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Introduction to Logic Gates; Author: Computer Science;https://www.youtube.com/watch?v=fw-N9P38mi4;License: Standard youtube license