Delmar's Standard Textbook Of Electricity
7th Edition
ISBN: 9781337900348
Author: Stephen L. Herman
Publisher: Cengage Learning
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Chapter 20, Problem 3RQ
How many degrees are the current and voltage out of phase in a pure capacitive circuit?
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Chapter 20 Solutions
Delmar's Standard Textbook Of Electricity
Ch. 20 - Can current flow through a capacitor?Ch. 20 - What two factors determine the capacitive...Ch. 20 - How many degrees are the current and voltage out...Ch. 20 - Does the current in a pure capacitive circuit lead...Ch. 20 - 5. A 30- capacitor is connected into a 240-V,...Ch. 20 - 6. A capacitor is connected into a 1250-V, 1000-Hz...Ch. 20 - 7. A capacitor is to be connected into a 480-V,...Ch. 20 - On the average, by what factor is the life...Ch. 20 - A capacitor is connected into a 277-V, 400-Hz...Ch. 20 - A capacitor has a voltage rating of 350 VAC. Can...
Ch. 20 - A utility company plans to connect a total of 20 F...Ch. 20 - What is the minimum AC voltage rating of each...Ch. 20 - What is the total current flow through the circuit...Ch. 20 - What is the minimum KVAR rating of each capacitor...Ch. 20 - You are working as an electrician in an industrial...Ch. 20 - You are working in an industrial plant. You have...Ch. 20 - Capacitive Circuits Fill in all the missing...Ch. 20 - A 4.7-F capacitor is connected to a 60-Hz power...Ch. 20 - A capacitor is connected to a 208-volt, 60-Hz...Ch. 20 - A 0.47-F capacitor is connected to a 240-volt...Ch. 20 - Three capacitors having capacitance values of...Ch. 20 - A capacitor has a capacitive reactance of 300 ...Ch. 20 - A pure capacitive circuit is connected to a...
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- 2. Using the approximate method, hand sketch the Bode plot for the following transfer functions. a) H(s) = 10 b) H(s) (s+1) c) H(s): = 1 = +1 100 1000 (s+1) 10(s+1) d) H(s) = (s+100) (180+1)arrow_forwardQ4: Write VHDL code to implement the finite-state machine described by the state Diagram in Fig. 1. Fig. 1arrow_forward1. Consider the following feedback system. Bode plot of G(s) is shown below. Phase (deg) Magnitude (dB) -50 -100 -150 -200 0 -90 -180 -270 101 System: sys Frequency (rad/s): 0.117 Magnitude (dB): -74 10° K G(s) Bode Diagram System: sys Frequency (rad/s): 36.8 Magnitude (dB): -99.7 System: sys Frequency (rad/s): 20 Magnitude (dB): -89.9 System: sys Frequency (rad/s): 20 Phase (deg): -143 System: sys Frequency (rad/s): 36.8 Phase (deg): -180 101 Frequency (rad/s) a) Determine the range of K for which the closed-loop system is stable. 102 10³ b) If we want the gain margin to be exactly 50 dB, what is value for K we should choose? c) If we want the phase margin to be exactly 37°, what is value of K we should choose? What will be the corresponding rise time (T) for step-input? d) If we want steady-state error of step input to be 0.6, what is value of K we should choose?arrow_forward
- : Write VHDL code to implement the finite-state machine/described by the state Diagram in Fig. 4. X=1 X=0 solo X=1 X=0 $1/1 X=0 X=1 X=1 52/2 $3/3 X=1 Fig. 4 X=1 X=1 56/6 $5/5 X=1 54/4 X=0 X-O X=O 5=0 57/7arrow_forwardQuestions: Q1: Verify that the average power generated equals the average power absorbed using the simulated values in Table 7-2. Q2: Verify that the reactive power generated equals the reactive power absorbed using the simulated values in Table 7-2. Q3: Why it is important to correct the power factor of a load? Q4: Find the ideal value of the capacitor theoretically that will result in unity power factor. Vs pp (V) VRIPP (V) VRLC PP (V) AT (μs) T (us) 8° pf Simulated 14 8.523 7.84 84.850 1000 29.88 0.866 Measured 14 8.523 7.854 82.94 1000 29.85 0.86733 Table 7-2 Power Calculations Pvs (mW) Qvs (mVAR) PRI (MW) Pay (mW) Qt (mVAR) Qc (mYAR) Simulated -12.93 -7.428 9.081 3.855 12.27 -4.84 Calculated -12.936 -7.434 9.083 3.856 12.32 -4.85 Part II: Power Factor Correction Table 7-3 Power Factor Correction AT (us) 0° pf Simulated 0 0 1 Measured 0 0 1arrow_forwardQuestions: Q1: Verify that the average power generated equals the average power absorbed using the simulated values in Table 7-2. Q2: Verify that the reactive power generated equals the reactive power absorbed using the simulated values in Table 7-2. Q3: Why it is important to correct the power factor of a load? Q4: Find the ideal value of the capacitor theoretically that will result in unity power factor. Vs pp (V) VRIPP (V) VRLC PP (V) AT (μs) T (us) 8° pf Simulated 14 8.523 7.84 84.850 1000 29.88 0.866 Measured 14 8.523 7.854 82.94 1000 29.85 0.86733 Table 7-2 Power Calculations Pvs (mW) Qvs (mVAR) PRI (MW) Pay (mW) Qt (mVAR) Qc (mYAR) Simulated -12.93 -7.428 9.081 3.855 12.27 -4.84 Calculated -12.936 -7.434 9.083 3.856 12.32 -4.85 Part II: Power Factor Correction Table 7-3 Power Factor Correction AT (us) 0° pf Simulated 0 0 1 Measured 0 0 1arrow_forward
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- A circularly polarized wave, traveling in the +z-direction, is received by an elliptically polarized antenna whose reception characteristics near the main lobe are given approx- imately by E„ = [2â, + jâ‚]ƒ(r. 8, 4) Find the polarization loss factor PLF (dimensionless and in dB) when the incident wave is (a) right-hand (CW) An elliptically polarized wave traveling in the negative z-direction is received by a circularly polarized antenna. The vector describing the polarization of the incident wave is given by Ei= 2ax + jay.Find the polarization loss factor PLF (dimensionless and in dB) when the wave that would be transmitted by the antenna is (a) right-hand CParrow_forwardjX(1)=j0.2p.u. jXa(2)=j0.15p.u. jxa(0)=0.15 p.u. V₁=1/0°p.u. V₂=1/0° p.u. 1 jXr(1) = j0.15 p.11. jXT(2) = j0.15 p.u. jXr(0) = j0.15 p.u. V3=1/0° p.u. А V4=1/0° p.u. 2 jX1(1)=j0.12 p.u. 3 jX2(1)=j0.15 p.u. 4 jX1(2)=0.12 p.11. JX1(0)=0.3 p.u. jX/2(2)=j0.15 p.11. X2(0)=/0.25 p.1. Figure 1. Circuit for Q3 b).arrow_forwardcan you show me full workings for this problem. the solution is - v0 = 10i2 = 2.941 volts, i0 = i1 – i2 = (5/3)i2 = 490.2mA.arrow_forward
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