You are given the following data about a virtual memory system: (a) The TLB can hold 512 entries and can be accessed in 1 clock cycle (1 nsec). (b) A page table entry can be found in 100 clock cycles or 100 nsec. (c) The average page replacement time is 9 msec. If page references are handled by the TLB 99% of the time, and only 0.01% lead to a page fault, what is the effective address-translation time?

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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You are given the following data about a virtual memory system:
(a) The TLB can hold 512 entries and can be accessed in 1 clock cycle (1
nsec).
(b) A page table entry can be found in 100 clock cycles or 100 nsec.
(c) The average page replacement time is 9 msec.
If page references are handled by the TLB 99% of the time, and only 0.01%
lead to a page fault, what is the effective address-translation time?

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