You are designing the memory hierarchy for a new processor. The access latency of main memory is 200 cycles. You have the following choices for the L2 design: 2MB, 16-way set-associative. Hit time = 30 cycles. %miss = 1% 1MB, 8-way set associative. Hit time = 20 cycles. %miss = 5% 512KB, 4-way set associative. Hit time = 15 cycles. %miss = 10% ● ● And the following choices for L1 design: 64KB, 8-way set associative. Hit time = 2 cycles. %miss = 4% 32KB, 4-way set associative. Hit Time = 1 cycle. %miss = 5% Question: Which cache design would you choose and why?
You are designing the memory hierarchy for a new processor. The access latency of main memory is 200 cycles. You have the following choices for the L2 design: 2MB, 16-way set-associative. Hit time = 30 cycles. %miss = 1% 1MB, 8-way set associative. Hit time = 20 cycles. %miss = 5% 512KB, 4-way set associative. Hit time = 15 cycles. %miss = 10% ● ● And the following choices for L1 design: 64KB, 8-way set associative. Hit time = 2 cycles. %miss = 4% 32KB, 4-way set associative. Hit Time = 1 cycle. %miss = 5% Question: Which cache design would you choose and why?
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Hello. Please answer the attached Computer Organization/Design question correctly & completely. Please show all of your work.
*If you answer the question correctly, I will give you a thumbs up. Thank you.
Transcribed Image Text:You are designing the memory hierarchy for a new processor. The access latency of main memory is 200
cycles. You have the following choices for the L2 design:
●
2MB, 16-way set-associative. Hit time = 30 cycles. %miss = 1%
1MB, 8-way set associative. Hit time = 20 cycles. %miss = 5%
512KB, 4-way set associative. Hit time = 15 cycles. %miss = 10%
●
And the following choices for L1 design:
64KB, 8-way set associative. Hit time = 2 cycles. %miss = 4%
32KB, 4-way set associative. Hit Time = 1 cycle. %miss = 5%
Question: Which cache design would you choose and why?
*
●
Please solve correctly and explain completely. Thank you.
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