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Write VHDL code for the FSM shown in the Figure below, using the style of code below. DN S1/0 DN S3/0 D DN DN D S2/0 S5/1 DN N D S4/1

Write VHDL code for the FSM shown in the Figure below, using the style of code below. DN S1/0 DN S3/0 D DN DN D S2/0 S5/1 DN N D S4/1

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Write VHDL code for the FSM shown in the Figure below, using the style of code below. DN S1/0 N DN S3/0 DN N DN DN D S2/0 S5/1 N D S4/1
Transcribed Image Text:Write VHDL code for the FSM shown in the Figure below, using the style of code below. DN S1/0 N DN S3/0 DN N DN DN D S2/0 S5/1 N D S4/1
1 LIBRARY ieee ; 2 USE ieee.std logic_1164.all; ENTITY simple IS PORT ( Clock, Resetn, w 3 4 : IN STD LOGIC; : OUT STD_LOGIC ) ; 6. END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C); SIGNAL y : State_type ; 7 8 10 BEGIN 11 PROCESS ( Resetn, Clock ) 12 BEGIN 13 IF Resetn = '0’ THEN 14 y <= A; ELSIF (Clock’EVENT AND Clock = '1’) THEN CASE y IS WHEN A => 15 16 17 18 IF w = '0' THEN 19 y <= A ; 20 ELSE y <= B ; END IF ; 21 22 23 WHEN B => IF w = '0' THEN y <= A ; ELSE 24 25 26 y <= C; END IF ; 27 28 29 WHEN C => 30 IF w = '0' THEN 31 y <= A ; 32 ELSE y <= C; END IF ; 33 34 35 END CASE ; END IF ; END PROCESS ; 36 37 38 z <= '1' WHEN y = C ELSE '0' ; 39 END Behavior ;
Transcribed Image Text:1 LIBRARY ieee ; 2 USE ieee.std logic_1164.all; ENTITY simple IS PORT ( Clock, Resetn, w 3 4 : IN STD LOGIC; : OUT STD_LOGIC ) ; 6. END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C); SIGNAL y : State_type ; 7 8 10 BEGIN 11 PROCESS ( Resetn, Clock ) 12 BEGIN 13 IF Resetn = '0’ THEN 14 y <= A; ELSIF (Clock’EVENT AND Clock = '1’) THEN CASE y IS WHEN A => 15 16 17 18 IF w = '0' THEN 19 y <= A ; 20 ELSE y <= B ; END IF ; 21 22 23 WHEN B => IF w = '0' THEN y <= A ; ELSE 24 25 26 y <= C; END IF ; 27 28 29 WHEN C => 30 IF w = '0' THEN 31 y <= A ; 32 ELSE y <= C; END IF ; 33 34 35 END CASE ; END IF ; END PROCESS ; 36 37 38 z <= '1' WHEN y = C ELSE '0' ; 39 END Behavior ;
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