Write a 2 to 4 decoder program using Verilog and Gate level modeling. Here is the source code but can you please write a working test bench for this. And if you are using a modelsim it would be a great help if you can simulate/trigger it to see if the program is really working. Thankyou so much! module decoder( D, A, B, enable ); output [0:3] D; // vector of 4 bits input A, B; input enable; wire Anot, Bnot, enableNot; not G1 (Anot, A), // note syntax: list of gates G2 (Bnot, B), // separated by , G3 (enableNot, enable); nand G4 (D[0], Anot, Bnot, enableNot ), G5 (D[1], Anot, B, enableNot ), G6 (D[2], A, Bnot, enableNot ), G7 (D[3], A, B, enableNot ); endmodule
Write a 2 to 4 decoder program using Verilog and Gate level modeling. Here is the source code but can you please write a working test bench for this. And if you are using a modelsim it would be a great help if you can simulate/trigger it to see if the program is really working. Thankyou so much! module decoder( D, A, B, enable ); output [0:3] D; // vector of 4 bits input A, B; input enable; wire Anot, Bnot, enableNot; not G1 (Anot, A), // note syntax: list of gates G2 (Bnot, B), // separated by , G3 (enableNot, enable); nand G4 (D[0], Anot, Bnot, enableNot ), G5 (D[1], Anot, B, enableNot ), G6 (D[2], A, Bnot, enableNot ), G7 (D[3], A, B, enableNot ); endmodule
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Write a 2 to 4 decoder program using Verilog and Gate level modeling.
Here is the source code but can you please write a working test bench for this.
And if you are using a modelsim it would be a great help if you can simulate/trigger it to see if the program is really working. Thankyou so much!
module decoder( D, A, B, enable );
output [0:3] D; //
input A, B;
input enable;
wire Anot, Bnot, enableNot;
not
G1 (Anot, A), // note syntax: list of gates
G2 (Bnot, B), // separated by ,
G3 (enableNot, enable);
nand
G4 (D[0], Anot, Bnot, enableNot ),
G5 (D[1], Anot, B, enableNot ),
G6 (D[2], A, Bnot, enableNot ),
G7 (D[3], A, B, enableNot );
endmodule
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