Write behavioral Verilog code for a module called “Sort2” (pictured below) with three inputs s, a, b and two outputs x, y. The module’s function is also described below; in the function table, a “–” represents a don’t care. Also the function table has s, a as inputs, but the outputs x, y are expressed in terms of the third input b. In words, the “function table” to the left translates to the following: When s = 0, the smallest value among a and b goes to x and the other value goes to y. When s = 1, the largest value among a and b goes to x and the other value goes to y.
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8. (a) Write behavioral Verilog code for a module called “Sort2” (pictured below) with three inputs s, a, b and two outputs x, y. The module’s function is also described below; in the function table, a “–” represents a don’t care. Also the function table has s, a as inputs, but the outputs x, y are expressed in terms of the third input b.
In words, the “function table” to the left translates to the following: When s = 0, the smallest value among a and b goes to x and the other value goes to y. When s = 1, the largest value among a and b goes to x and the other value goes to y.
(b) Structurally connect copies (or instantiations) of the module Sort2 to construct the module Bitonic with four inputs a0,a1,a2,a3 and four outputs z0,z1,z2,z3 shown below; each box in the figure below represents an instantiation of Sort2. Further, the inputs and outputs of the instantiations are located as in the figure above; namely, input to the top of the box is s, top input to the side is a, bottom output is y and so on.
(c) Try out the following values for input ha0,a1,a2,a3i on the module Bitonic. Determine the outputs and try to guess what module Bitonic does. Values of A to try out: <1,0,1,0> , <0,1,0,0> , <1,1,0,1> , <1,1,1,0>
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