When a control hazard occurs, what usually happens is to simply insert 3 bubbles. But, why does the first image says the penalty is only one? What's the case? I would like to know more about control hazards and its solutions, that's the question. I would like to know about the penalties in the case we assume a branch will be always takes, always untaken, and when we do not assume anything. For better understanding, if possibly, I would like to know about what happens in the stages (IF, ID, EX, MEM, WB) too, considering 5 stage pipeline. Also, please clarify if we need forwarding. Programexecutionorder(in instructions)add x4, x5, x6beq x1, x0, 40Time200 400 600 800or x7, x8, x9Instructionfetch200 psDataaccessReg ALUReg ALUInstructionfetchRegRegCoubble Coubble Coubble Coubble CoubbleInstructionfetchReg ALU400 psDataaccessFIGURE 4.29 Pipeline showing stalling on every conditional branch as solution to controlhazards. This example assumes the conditional branch is taken, and the instruction at the destination ofthe branch is the or instruction. There is a one-stage pipeline stall, or bubble, after the branch. In reality, theprocess of creating a stall is slightly more complicated, as we will see in Section 4.8. The effect on performance,however, is the same as would occur if a bubble were inserted.1000 1200 1400DataaccessReg

Answered: When a control hazard occurs, what…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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When a control hazard occurs, what usually happens is to simply insert 3 bubbles. But, why does the first image says the penalty is only one? What's the case?

I would like to know more about control hazards and its solutions, that's the question. I would like to know about the penalties in the case we assume a branch will be always takes, always untaken, and when we do not assume anything. For better understanding, if possibly, I would like to know about what happens in the stages (IF, ID, EX, MEM, WB) too, considering 5 stage pipeline. Also, please clarify if we need forwarding.

Program
execution
order
(in instructions)
add x4, x5, x6
beq x1, x0, 40
Time
200 400 600 800
or x7, x8, x9
Instruction
fetch
200 ps
Data
access
Reg ALU
Reg ALU
Instruction
fetch
Reg
Reg
Coubble Coubble Coubble Coubble Coubble
Instruction
fetch
Reg ALU
400 ps
Data
access
FIGURE 4.29 Pipeline showing stalling on every conditional branch as solution to control
hazards. This example assumes the conditional branch is taken, and the instruction at the destination of
the branch is the or instruction. There is a one-stage pipeline stall, or bubble, after the branch. In reality, the
process of creating a stall is slightly more complicated, as we will see in Section 4.8. The effect on performance,
however, is the same as would occur if a bubble were inserted.
1000 1200 1400
Data
access
Reg

Expert Solution

Step 1

Dependencies in a pipelined processor

There are mainly three types of dependencies possible in a pipelined processor. These are :
1) Structural Dependency
2) Control Dependency
3) Data Dependency

These dependencies may introduce stalls in the pipeline.

Stall: A stall is a cycle in the pipeline without new input.

Structural dependency

This dependency arises due to the resource conflict in the pipeline. A resource conflict is a situation when more than one instruction tries to access the same resource in the same cycle. A resource can be a register, memory, or ALU.

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