What is the value in count if input sel=10 after the third rising edge of clock based on the following Verilog code: module Stest( input wire clk, input wire [1:0] sel, output reg out = 0); integer count=0; always @ (posedge clk) begin count = count + 1; case (sel) 0 : out = ~out; 1 : if (count == 2) begin out = ~out; count = 0; end 2 : if (count == 4) begin out = ~out; count = 0; end 3 : if (count == 8) begin out = ~out; count = 0; end default: count = 0; endcase end endmodule
What is the value in count if input sel=10 after the third rising edge of clock based on the following Verilog code:
module Stest(
input wire clk, input wire [1:0] sel, output reg out = 0);
integer count=0;
always @ (posedge clk) begin
count = count + 1;
case (sel)
0 : out = ~out;
1 : if (count == 2) begin
out = ~out;
count = 0;
end
2 : if (count == 4) begin
out = ~out;
count = 0;
end
3 : if (count == 8) begin
out = ~out;
count = 0;
end
default: count = 0;
endcase
end
endmodule
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