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We wish to design the CE stage shown below for a voltage gain of 20. What is the minimum allowable supply voltage if Q, must remain in the active mode? Assume Re= 40 k, V=0 and VBE = 0.78 V.

We wish to design the CE stage shown below for a voltage gain of 20. What is the minimum allowable supply voltage if Q, must remain in the active mode? Assume Re= 40 k, V=0 and VBE = 0.78 V.

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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We wish to design the CE stage shown below for a voltage gain of 20. What is the minimum allowable supply voltage if Q, must remain in the active mode? Assume Rc= 40 k2, V =0 and VBE = 0.78 V. (, - 1.a in ve... hast vA .. 17. Vcc= 2.5 V Rc o Vout Vin A) 1.3 V B) 1.7 V C) 1.5 V O D) 1.1 V
Transcribed Image Text:We wish to design the CE stage shown below for a voltage gain of 20. What is the minimum allowable supply voltage if Q, must remain in the active mode? Assume Rc= 40 k2, V =0 and VBE = 0.78 V. (, - 1.a in ve... hast vA .. 17. Vcc= 2.5 V Rc o Vout Vin A) 1.3 V B) 1.7 V C) 1.5 V O D) 1.1 V
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