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Computer Engineering
using Verilog: you will demonstrate that NOR is a universal gate by making a NAND gate using only NOR gates. a. Create a Verilog file called NANDusingNOR.v i. In it, create a module called NORgate that accepts two inputs A, and B; and gives an output Q which is the result of A nor B. ii. In it, also create a module called NANDusingNor and use a series of NOR gates to create a NAND gate. b. Create a testbench called NANDusingNOR_tb.v. Simulate that it works by testing every combination of A and B.

using Verilog: you will demonstrate that NOR is a universal gate by making a NAND gate using only NOR gates. a. Create a Verilog file called NANDusingNOR.v i. In it, create a module called NORgate that accepts two inputs A, and B; and gives an output Q which is the result of A nor B. ii. In it, also create a module called NANDusingNor and use a series of NOR gates to create a NAND gate. b. Create a testbench called NANDusingNOR_tb.v. Simulate that it works by testing every combination of A and B.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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using Verilog:

you will demonstrate that NOR is a universal gate by making a NAND gate using only NOR gates.

a. Create a Verilog file called NANDusingNOR.v

i. In it, create a module called NORgate that accepts two inputs A, and B; and gives an output Q which is the result of A nor B.

ii. In it, also create a module called NANDusingNor and use a series of NOR gates to create a NAND gate.

b. Create a testbench called NANDusingNOR_tb.v. Simulate that it works by testing every combination of A and B. 

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