Upload answer sheets A computer manufacturing company is involved in memory design. They need to develop a proper plan before entering into the production part. The objective is to design a memory based on five partitions of varied sizes. The sizes are as mentioned below: 100 KB, 200 KB, 300KB, 400KB and 500 KB. With these varied partition sizes available, the allocation should be made to four processes of sizes 357KB, 212KB, 426 KB and 468 KB. The three available allocation algorithms called First Fit, Best Fit and Worst Fit, perform the allocation of the processes.

Upload answer sheets A computer manufacturing company is involved in memory design. They need to develop a proper plan before entering into the production part. The objective is to design a memory based on five partitions of varied sizes. The sizes are as mentioned below: 100 KB, 200 KB, 300KB, 400KB and 500 KB. With these varied partition sizes available, the allocation should be made to four processes of sizes 357KB, 212KB, 426 KB and 468 KB. The three available allocation algorithms called First Fit, Best Fit and Worst Fit, perform the allocation of the processes.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

A computer manufacturing company is involved in memory design. They need to develop a proper plan before entering into the production part. The objective is to design a memory based on five partitions of varied sizes. The sizes are as mentioned below: 100 KB, 300Kb, 500KB and 600 KB. With these varied partition sizes available, the allocation should be made to four processes of sizes 112KB, 212KB, 426 KB and 462 KB. The three available allocation algorithms called First Fit, Best Fit and Worst Fit, perform the allocation of the processes
SUBJECT: OPERATING SYSTEM
A computer system contains a big endian byte addressable memory system with 8 separate memory modules. Each memory module is 32 bits wide and contains 134217728 cells. Cells within each memory module are numbered 0 through 134217727. a) If the memory employs high order interleaving, what is the 32-bit memory address of cell 1048578 within module 3? b) If the high order interleaved memory uses little-endian instead of big-endian storage order, what is the 32-bit memory address of cell 511 within module 1? c) If the memory employs low order interleaving, what is the 32-bit memory address of byte 1048575 within module 2? Bytes are numbered starting from 0. Express the address in hex. d) What is the main advantage of using low-order interleaved memory compared to using high-order interleaved memory?
A computer employs RAM chips of 512 x 16 and ROM chips of 1024 x 8. The computer system needs 4K bytes of RAM and 2K bytes of ROM along with interface unit of 128 registers each. A memory mapped I/0 configuration is used. The two higher order bits are assigned for RAM, ROM and interface as 00, 01 and 10 respectively. a) How many RAM and ROM chips are needed
Figure 1 shows the design of a 6116 static CMOS RAM that can store 2K bytes of data. The memory has 16384 cells, arranged as a 128X128 memory matrix. The 11 address lines, which are needed to address 211 bytes of data, are divided into two groups. Lines A10 through A4 select one of the 128 rows in the matrix. Lines A3 through A0 select 8 columns in the matrix at a time since there are 8 data lines. The data outputs from the matrix go through tri-state buffers before connecting to the data I/O lines. These buffers are disabled except when reading from the memory. Table 1 shows the truth table of the SRAM block. Model the 6116 SRAM block using VHDL. You should incorporate the timing specifications of the 6116 block in your VHDL model by looking at its datasheet. A10 Memory Matrix Row Decoder 128 X 128 A4 ... 107 Column I/0 Input Data Column Decoder Control A3 A2 A1 Ao OE D WE CS Figure 1. Table 1. CS OE WE Mode /0 pins X Not selected High-Z High-Z Data out X Output disabled Read Write L…
D part only
1. Computer Memory (a) Describe in detail the difference between memory bandwidth and memory latecy. (b) Describe in detail and give a small source code example of the difference in spatial and temporal locality. (c) Describe in detail and give a diagram for virtual memory. (d) Describle in detail the difference in SRAM and DRAM.
Design a memory map for a system with 64 K of memory space, a 16-bit address bus, and a 8-bit data bus. The system needs to meet the following design requirements: The system needs 20 K of RAM, organized in a contiguous block starting at address 0x1000 . The system needs RAM filling the memory range from 0xA000 to 0xCFFF (inclusive) Your design must be subject to the following constraints in terms of access to memory chips: You can use a maximum of two (2) 8 K×8 RAM chips. You can use a maximum of two (2) 4 K×8 RAM chips. You can use a maximum of two (2) 8 K×8 ROM chips. You can use a maximum of two (2) 4 K×4 ROM chips.
A large endian byte addressed memory system with eight distinct memory modules is included in a computer system. Each memory module has 134217728 cells and is 32 bits wide. a) What is the 32-bit memory address of cell 1048578 in module 3 if the memory uses high order interleaving? b) What is the 32-bit memory address of byte 1048575 inside module 2 if the memory uses high order interleaving? c) What is the 32-bit memory address of cell 511 inside module 1 if the high order interleaved memory utilises little endian storage order instead of big endian storage order?
You have been contracted to design a memory system for a computer. Assuming the processor has 20 address lines, determine the number of 16 KB memories that can be placed (without overlapping) in the memory space of a processor.
A computer employs RAM chips of 512 x 8 and ROM chips of 256 x 8. The computer system needs1K bytes of RAM, 2K bytes of ROM, and eight interface units, each with 2 registers. A memory-mapped1/0 configuration is used. The two highest-order bits of the 16 bit address bus are assigned 10 for RAM,11 for ROM, and 00 for interface registers.a. How many RAM and ROM chips are needed?b. Draw a memory-address map for the system.c. Give the address range in hexadecimal for RAM, ROM, and interface.
5. Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. (a) Suppose all instructions and operands are one byte long, by what factor do the maximum data transfer rates differ?