1d) The timing for a particular cache is as follows: Checking the cache takes 1 cycle. If there is a hit, the data is returned to the CPU at the end of the first cycle. If there is a miss, it takes additional ten (10) cycles to retrieve the word from the main memory, store it in the cache and return it to the CPU. If we want an average access time of 1.4 cycles, what should be the minimum possible value of the cache hit ratio?
1d) The timing for a particular cache is as follows: Checking the cache takes 1 cycle. If there is a hit, the data is returned to the CPU at the end of the first cycle. If there is a miss, it takes additional ten (10) cycles to retrieve the word from the main memory, store it in the cache and return it to the CPU. If we want an average access time of 1.4 cycles, what should be the minimum possible value of the cache hit ratio?
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
Related questions
Question
D part only
![la) Draw a clearly labelled diagram of memory hierarchy indicating:
(i) The correct order of SPEED, from the fastest to the slowest
(ii) The correct order of COST, from the most expensive to the cheapest
(iii) The correct order of SIZE, from the largest to the smallest
(iv) The correct order of VOLATILITY, from the most volatile to the least volatile
1b) Which of the memories in the memory hierarchy is best suited for holding each of the
following kinds of data?
(i) Data that are being used right now.
(ii) Data that are being used by a program that is currently running.
(iii)Data that need to be saved even when the computer's power is turned
off.
(iv) Data that are about to be used, or have just been used.
1c) A computer has a 256 KByte, 4-way set associative, write back data cache with the block
size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Calculate the
number of bits for the Tag, the set-index, and the word-offset.
How many blocks of data does the main memory have?
[Hint: Memory is Byte Addressable]
1d) The timing for a particular cache is as follows: Checking the cache takes 1 cycle. If there is
a hit, the data is returned to the CPU at the end of the first cycle. If there is a miss, it takes
additional ten (10) cycles to retrieve the word from the main memory, store it in the cache and
return it to the CPU. If we want an average access time of 1.4 cycles, what should be the
minimum possible value of the cache hit ratio?](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F524d2751-fdc5-47ff-8952-3c1c230d3b82%2Ff6cfd6ec-6ad5-430c-b90d-af0d36f0f27a%2Foo4e1h_processed.png&w=3840&q=75)
Transcribed Image Text:la) Draw a clearly labelled diagram of memory hierarchy indicating:
(i) The correct order of SPEED, from the fastest to the slowest
(ii) The correct order of COST, from the most expensive to the cheapest
(iii) The correct order of SIZE, from the largest to the smallest
(iv) The correct order of VOLATILITY, from the most volatile to the least volatile
1b) Which of the memories in the memory hierarchy is best suited for holding each of the
following kinds of data?
(i) Data that are being used right now.
(ii) Data that are being used by a program that is currently running.
(iii)Data that need to be saved even when the computer's power is turned
off.
(iv) Data that are about to be used, or have just been used.
1c) A computer has a 256 KByte, 4-way set associative, write back data cache with the block
size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Calculate the
number of bits for the Tag, the set-index, and the word-offset.
How many blocks of data does the main memory have?
[Hint: Memory is Byte Addressable]
1d) The timing for a particular cache is as follows: Checking the cache takes 1 cycle. If there is
a hit, the data is returned to the CPU at the end of the first cycle. If there is a miss, it takes
additional ten (10) cycles to retrieve the word from the main memory, store it in the cache and
return it to the CPU. If we want an average access time of 1.4 cycles, what should be the
minimum possible value of the cache hit ratio?
Expert Solution
This question has been solved!
Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.
Step by step
Solved in 2 steps with 1 images
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY