Need all three parts 1. Greedy Pairwise Merge.Two sorted files containing sSn and sm records respectively can be merged together to obtain one sortedfile in time O(8n + Sm). When more than two sorted files are to be merged together, the merge canbe accomplished by repeatedly merging sorted files in pairs. Thus, if four files X; of size si, 1 sis 4are to be merged we could first merge X1 and X2 to get a file Y1. Then we could merge Yı and X3to get Y2. Finally, Y2 and X4 can be merged to obtain the desired sorted file. Alternatively, we couldfirst merge X1 and X2 getting Y1, then merge X3 and X4 getting Y2 and finally Y1 and Y2 getting thedesired sorted file.Given n sorted files X; of sizes s;, 1 < i < n there are many ways in which to pairwise merge theminto a sorted file. Different pairings require differing amounts of computing time.(a) Give C/C++ pseudocode for a greedy algorithm to determine an optimal (i.e., one requiring thefewest comparisons) way to pairwise merge n sorted files together.(b) How much time does your algorithm require?(c) Does your algorithm always find the optimal pairwise merge? Either sketch a proof or give acounter-example.

1. a . pseudocode int mergeFile(int files[]) priority_queue que; //min priority queue int count=0;…

Two sorted files containing sn and sm records respectively can be merged together to obtain one sorted file in time O(sn + 8m). When more than two sorted files are to be merged together, the merge can be accomplished by repeatedly merging sorted files in pairs. Thus, if four files X; of size si, 1 < i < 4 are to be merged we could first merge X1 and X2 to get a file Y1. Then we could merge Y1 and X3 to get Y2. Finally, Y2 and X4 can be merged to obtain the desired sorted file. Alternatively, we could first merge X1 and X2 getting Yı, then merge X3 and X4 getting Y2 and finally Yı and Y2 getting the desired sorted file. Given n sorted files X; of sizes si, 1 < i < n there are many ways in which to pairwise merge them into a sorted file. Different pairings require differing amounts of computing time. (a) Give C/C++ pseudocode for a greedy algorithm to determine an optimal (i.e., one requiring the fewest comparisons) way to pairwise merge n sorted files together. (b) How much time does your algorithm require? (c) Does your algorithm always find the optimal pairwise merge? Either sketch a proof or give a counter-example.

Two sorted files containing sn and sm records respectively can be merged together to obtain one sorted file in time O(sn + 8m). When more than two sorted files are to be merged together, the merge can be accomplished by repeatedly merging sorted files in pairs. Thus, if four files X; of size si, 1 < i < 4 are to be merged we could first merge X1 and X2 to get a file Y1. Then we could merge Y1 and X3 to get Y2. Finally, Y2 and X4 can be merged to obtain the desired sorted file. Alternatively, we could first merge X1 and X2 getting Yı, then merge X3 and X4 getting Y2 and finally Yı and Y2 getting the desired sorted file. Given n sorted files X; of sizes si, 1 < i < n there are many ways in which to pairwise merge them into a sorted file. Different pairings require differing amounts of computing time. (a) Give C/C++ pseudocode for a greedy algorithm to determine an optimal (i.e., one requiring the fewest comparisons) way to pairwise merge n sorted files together. (b) How much time does your algorithm require? (c) Does your algorithm always find the optimal pairwise merge? Either sketch a proof or give a counter-example.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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For a Turing machine M, (M) refers to the binary representation of M. For a Turing machine M, L(M) contains the set of all strings accepted by M. For a Turing machine M and an input x = {0,1}*, Steps(M, x) refers to the number of steps taken by M to execute on x before it halts. Here, one step of execution of M on x = one movement (left or right) of the tape head. For a Turing machine M and an input x = {0,1}*, we define the following: ReachCells(M,x) = {i : M reaches ith tape cell when M is executed on x} Informally, it contains all locations on the tape that are visited when M is ecuted on x. The leftmost location on the tape is the first tape cell, the location next to it is the second tape cell, and so on. A string w₁ is an anagram of w2 if w₁ can be obtained by rearranging the alphabets of w2. Formally, if w₁ is an n length string, wê is called an anagram of w₁ if there exists a permutation à on n elements such that π(w₁) = W2.
Use Keil ARM assembly to check whether an N × N matrix is a magic square. A magic square is an N × N matrix in which the sums of all rows, column, and the two diagonals add up to N (N2 + 1)/2. All matrix entries are unique numbers from 1 to N2. Register r1 will hold N. The matrix starts at location 0x20000010 (Base address) and ends at location (Base address + N2). It is assumed that all numbers are bytes, consider the 4-byte size of integers.Use the included picture The numbers 16, 3, 2, 13 will be stored at first four addresses, respectively. The numbers 5, 10, 11, and 8 would be stored at next four addresses, etc. If the matrix is a magic square, register r8 will be set (R8 should have a value 1) upon completion; otherwise, it will be cleared to 0. Please don't make it too complicated, if you can, I want to learn what I am writing down, if possible. Thank you!
one Mil Q#1: Consider the instruction: add $2, $1, $3 What registers will be written and what registers will be read to execute this instruction? Registers to be written Registers to be read Q#2: Since we only support the add instruction, we don't care much for opcodes and funct codes and shamts. Therefore, suppose our programs are given to the processor as three inputs RD, RS, and RT. Each instruction executes within 1 clock periods Translate the following program to the RW, RS, RT inputs (in binary). clock period RD RS 1 2 3 4 RS RT Program add $2, $1, $3 add $0, $0, $1 add $1, $2, $2 add $1, $1, $1 Q#3: Design the single-cycle cessor datapath (only ID, EX and WB stages) using the mong different components. following datapath components.rly s the number of bits to be transferred in each data line and data bus connectio RD cik Registers RA RB RW BusA RegWrite Bus8 Bus W ALU zero ALU result overflow RT ALUOP
A 1983 IEEE proceedings, volume 71 essay is reproduced here. An early OSI Layer whitepaper. This document is also available in PDF format. Now answer: In order to coordinate the efforts of many parties, the OSI Reference Model has proved to be incredibly effective. The author describes an issue that was solved.b) What are the OSI architectural components?In the OSI model, the OSI model recognises three kinds of N-on-N-1 construction and two types of error control. Explain \sbriefly.d) How did SC16 handle it?In order to split the challenge down into smaller, more manageable difficulties, layers were selected.
i want all the staps Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of "6" addressing modes, and it has “50" computer registers. The computer supports instructions, where each instruction consists of following fields: • Mode • Operation code • Register • Register • Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
Consider a processor that uses a 48-bit virtual memory address. The main memory installed onthe system is 4GB. Page size is set to be 32KB. Determine the following:I. Address space of virtual memory and physical memory. II. Total Number of virtual pages and the total physical pagesIII. How many bits are necessary to store (i) Page Table entry and (ii) TLB entry, consideringthe TLB entry stores valid, reference and dirty bits.IV. What is the size of the page table? And how many pages of memory is needed to storethe entire Page table? What fraction of physical memory is needed to store the entirepage table?
The hardware used to replicate Pep/9 has 64K memory. But what is its purpose? So far, just 0x0030 of memory has been written. What gives with all that additional RAM, then? How does each memory region in Pep/9 know what to do with it? Another viewpoint There have only been "global" variables utilised. What impact would using "local" variables have? What distinguishes them? (Think of "stack").
Problem Title: Design and implement a digital processing-based speech quality enhancement system to improve the signal to noise ratio (SNR) of recorded speech signal. Problem Description: Design and implement a digital processing-based speech quality enhancement system for voice signal recorded by you. The details of the design constraints are as follows: 1. Required to record Voice in a noisy environment and perform statistical analysis of the recorded audio signal to find: o Mean o Standard Deviation o Variance o No of Zero Crossings o SNR o Frequency spectrum 2. Based on analysis, design and implement a digital signal processing system for the enhancement of speech signal.
Convert the following PDA to CFG: ({g, p}. {0, 1}, {Zo, X},&, q, Zo, {p}) P = 1. d(q,0, Zn) = {(q, X Za)}. 2. 64.0, X) — {(ч, XX)). 3. 8(4,1, X) = {(q, X)}. 4. 8(g, €, X) = {(p, e)}. 5. 8(p, e, X) = {(p,e)}. 6. 6(р, 1, X) %3D {(p, XX)}. 7. 6(р, 1, 20) 3 {(p, e)}.
The simulated Pep/9 hardware has 64K of memory. But how is it put to use? So far, just 0x0030 memory has been written. So, what's the deal with all of that additional RAM? Pep/9 knows what to do with each memory location. Another viewpoint Only "global" variables were used. What effect would using "local" variables have? What distinguishes them? (Think "stack").