Answered: This is a practice question (not a…

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...

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This is a practice question (not a graded assignment) from my Digital Systems lab course.

The first part was to create a schematic from 2:4 decoder truth table using only NAND gates. This was done, as you can see, and is correct. Now, we're supposed to write the VHDL code for a module named "2x4_Decoder" that implements the NAND gate schematic using gate terminology and the labels from the schematic, as well as a test bench for it. I'm completely lost. All we've done so far is simple individual gates, nothing with multiple gates or connections (it's our second week in VHDL). If I could see a complete, working example for this, I could probably figure out other implementation configurations.

Thank you for your assistance.

Create a Design Source for the 2:4 decoder module and implement your NAND gate schematic as a
structural architecture.
A
O
A NOT
A NOT OUT
B NOT
B NOT OUT
Y3
Y2 1
Y1 1
YO 1
Y3 1 OUT
Y2 1 OUT
Y1 1 OUT
YO 1 OUT
Y3 2
Y2 2
Y1 2
YO 2
Y3
Y2
Y1
YO

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