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The network Fig. 2.42 is an AND gate for positive logic. That is, the E-V level of Fig. 2.42 is assigned a "1" for Boolean algebra and the 0-V input is assigned a "0." An AND gate is such that the output voltage level will be a 1 if both inputs is a 1. The output is a 0 if any input is at the 0 level. Determine the ouput voltage Va across R given that E 2.6 k2. = 10 V, E = 0 V, E, = 10 V and R %3D %3D (0) Si Select the correct answer A 1.86 V Si E 10 V B 9.3 V C 7.44 V D 46.5 V E 6.51 V FIG. 2.42 Positive logic AND gate. Answer this question Determine Ip, of the parallel diode configuration of Fig. 2.28 given that E = 18 V and R = 210 n. Select the correct answer A 12.357 mA B 61.786 mA C 24.714 mA D 4.119 mA G. 13 E 41.19 mA

The network Fig. 2.42 is an AND gate for positive logic. That is, the E-V level of Fig. 2.42 is assigned a "1" for Boolean algebra and the 0-V input is assigned a "0." An AND gate is such that the output voltage level will be a 1 if both inputs is a 1. The output is a 0 if any input is at the 0 level. Determine the ouput voltage Va across R given that E 2.6 k2. = 10 V, E = 0 V, E, = 10 V and R %3D %3D (0) Si Select the correct answer A 1.86 V Si E 10 V B 9.3 V C 7.44 V D 46.5 V E 6.51 V FIG. 2.42 Positive logic AND gate. Answer this question Determine Ip, of the parallel diode configuration of Fig. 2.28 given that E = 18 V and R = 210 n. Select the correct answer A 12.357 mA B 61.786 mA C 24.714 mA D 4.119 mA G. 13 E 41.19 mA

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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Answer this question The network Fig. 2.42 is an AND gate for positive logic. That is, the E-V level of Fig. 2.42 is assigned a "1" for Boolean algebra and the 0-V input is assigned a "0." An AND gate is such that the output voltage level will be a 1 if both inputs is a 1. The output is a 0 if any input is at the 0 level. Determine the ouput voltage Vo across R given that E = 10 V, E = 0 V, E, = 10 V and R = 2.6 kn. (0) Si E OV 1. Select the correct answer D, Si A 1.86 V E 10 V B 9.3 V D C 7.44 V D 46.5 V E 6.51 V FIG. 2.42 Positive logic AND gate. Answer this question Determine Ip, of the parallel diode configuration of Fig. 2.28 given that E = 18 V and R= 210 N. Select the correct answer A 12.357 mA B 61.786 mA C 24.714 mA D 4.119 mA RG.3.3 E 41.19 mA
Transcribed Image Text:Answer this question The network Fig. 2.42 is an AND gate for positive logic. That is, the E-V level of Fig. 2.42 is assigned a "1" for Boolean algebra and the 0-V input is assigned a "0." An AND gate is such that the output voltage level will be a 1 if both inputs is a 1. The output is a 0 if any input is at the 0 level. Determine the ouput voltage Vo across R given that E = 10 V, E = 0 V, E, = 10 V and R = 2.6 kn. (0) Si E OV 1. Select the correct answer D, Si A 1.86 V E 10 V B 9.3 V D C 7.44 V D 46.5 V E 6.51 V FIG. 2.42 Positive logic AND gate. Answer this question Determine Ip, of the parallel diode configuration of Fig. 2.28 given that E = 18 V and R= 210 N. Select the correct answer A 12.357 mA B 61.786 mA C 24.714 mA D 4.119 mA RG.3.3 E 41.19 mA
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