the first stage. ven: R1 = 33 kn, R2 = 8.2 kN, RC = 3.3 kO, RE = 1 kO, Beta = 175, Vcc = 15 V %3D ... Rc Rc R1 Rc R1 R1 Vi Q1 오2 Q3 RL. R2 R2 {R2 REJ RE1 SREZ-

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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If the multistage amplifier is driven by a 1 µV saurce and the last stage is loaded with an RL = 20 ko, determine the expected voltage gain
of the first stage.
Given: R1 = 33 kO, R2 = 8.2 kQ, RC = 3.3 kQ, RE = 1 ko, Beta = 175, Vcc = 15 V
Vga
Rc
Rc
R1
Rc
R1
R1
v.
Vi
{Q1
Q2
Q3
RL.
R2
R2
RE1
RE2
R2
REJ
Transcribed Image Text:If the multistage amplifier is driven by a 1 µV saurce and the last stage is loaded with an RL = 20 ko, determine the expected voltage gain of the first stage. Given: R1 = 33 kO, R2 = 8.2 kQ, RC = 3.3 kQ, RE = 1 ko, Beta = 175, Vcc = 15 V Vga Rc Rc R1 Rc R1 R1 v. Vi {Q1 Q2 Q3 RL. R2 R2 RE1 RE2 R2 REJ
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