Symmetrical CMOS Inverter Delays* (ns) VSAT Unlimited Tp 0.71 0.89 1.58 1.74 1.74 *Symmetrical CMOS inverter circuit in Fig. 7.12 with C= 0.2 pF
Symmetrical CMOS Inverter Delays* (ns) VSAT Unlimited Tp 0.71 0.89 1.58 1.74 1.74 *Symmetrical CMOS inverter circuit in Fig. 7.12 with C= 0.2 pF
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Question
(a) What W/L ratios are required for the NMOS and PMOS transistors to achieve a propagation delay of 0.71 ns for the VSAT = 1 V case in Table ? (b) What W/L ratios are required for the NMOS and PMOS transistors to achieve rise and fall times of 1.58 ns for the VSAT = 1 V case?
Expert Solution
Step 1
(a) The current (W/L ratios) needs to be scaled by the delay change. For reducing the delay, the current is needed to increase.
Given
Propagation delay
Assume the values,
From the given table, for the symmetrical CMOS inverter propagation delay values.
The propagation delay at is 0.89
Step 2
The expression for width-to-length is,
The expression for width-to-length is,
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