Answered: Symmetrical CMOS Inverter Delays* (ns)…

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

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Question

(a) What W/L ratios are required for the NMOS and PMOS transistors to achieve a propagation delay of 0.71 ns for the V_SAT = 1 V case in Table ? (b) What W/L ratios are required for the NMOS and PMOS transistors to achieve rise and fall times of 1.58 ns for the V_SAT = 1 V case?

Symmetrical CMOS Inverter Delays* (ns)
VSAT
Unlimited
Tp
0.71
0.89
1.58
1.74
1.74
*Symmetrical CMOS inverter circuit in Fig. 7.12 with C= 0.2 pF

Expert Solution

Step 1

(a) The current (W/L ratios) needs to be scaled by the delay change. For reducing the delay, the current is needed to increase.

Given

Propagation delay $τ = 0.71 ns$

Assume the values,

$\begin{array}{rcl} M_{P} & = & \frac{5}{1} \\ M_{N} & = & \frac{2}{1} \end{array}$

From the given table, for the symmetrical CMOS inverter propagation delay values.

The propagation delay $τ_{p}$ at $V_{S A T} = 1 V$ is 0.89

Step 2

The expression for width-to-length ${(\frac{W}{L})}_{N}$ is,

$\begin{array}{rcl} {(\frac{W}{L})}_{N} & = & \frac{τ_{p}}{τ} (M_{N}) \\ = & \frac{0.89}{0.71} (\frac{2}{1}) \\ = & (\frac{2.51}{1}) \end{array}$

The expression for width-to-length ${(\frac{W}{L})}_{P}$ is,

$\begin{array}{rcl} {(\frac{W}{L})}_{P} & = & \frac{τ_{p}}{τ} (M_{P}) \\ = & \frac{0.89}{0.71} (\frac{5}{1}) \\ = & (\frac{6.27}{1}) \end{array}$

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