Suppose an input error signal, Figure 1, is applied to a PID-Controller with k, = 2, k; = 2 s, and ka = 2 s. Calculate the controller output voltage at t = 4 S. 10 11 12 Time (s) Error (%)
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- Q2) A) Based on the count sequence and decoding operations of 74LS90S ICs shown in Figure below. Q2) B) Use the SAR ADC to convert the analog voltage of (7.28 V) to 8-bit binary. If (VREF = 10V), determine the final %3D binary answer and the percent error. 01011101, 0.1974588% 11011101, 0.1974588% 01011111, 0.1974588% 01111101, 0.1974588%B6Q1. Design asynchronous (ripple ) binary counter and timing diagram for the following sequence (0,1,2,3,4,5) Q2. Determine the resolution expressed as a percentage of 16-bit DAC.
- The input waveform shown in the figure below is applied to an inverter, which is used to operate a light on a control circuit. Draw the timing diagram of the output waveform in proper relation to the input.Q1. Using a Finite State Machine, Design a counter that: Count: 000, 010, 111, 011, 110, 100, 001, 101, 000, 010, 111, .. the Reset: Asynchronous active-low input signal. It initializes the count to "000". The input E: Synchronous input that increases the count when it is set to '1'. The output z: It becomes '1' when the count is 101. Provide the State Diagram in any representation. reset E. clock CounterAssuming that a 4-bit ADC accepts analog input ranging from 0 to 6 volts, solve the following: a) The number of quantization levels is b) The step size of the quantizer is c) For a signal level of 3.25V, the quantized value is and the binary code of that quantized value is volt volts
- Solve i) ii) and iii) only Show all the details with clear explanationA 9 bit asynchronous counter has a 128 - kHz clock signal applied. i) What the mod Number of this counter ? ii) What will be the frequency at the MSB output ? iii) Assume that the counter starts at zero.What will be the count after 6.15 input pulse?A certain successive approximation type 8 bit ADC can handle input voltages in the range 0 – 8V. Find, i. The resolution of the ADC. ii. The conversion speed of the ADC for a 1MHZ clock.
- (a) Figure Q4(a)(i) shows two unit of 74LS293 (4-bit binary counter) configured to generate multiple clock source. Referring to the internal circuit diagram of this IC shown in Figure Q4(a)(ii), obtain the frequency at fi, f2 and f3. Q4 fi f2 f3 1 Q4 2 100 Hz- (10) CP (8) (10) CP Q4 (8) (11) CP (4) (11) CP (4) Q2 Q2 (5) (5) Q1 Q1 (12) MR & (12) MR, & (9) QO (9) QO (13) MR (13) MR Figure Q4(a)(i)A 9-bit asynchronous counter has a 128-kHz clock signal applied. (1) What is the MOD number of this counter? MOD number = (ii) What will be the frequency at the MSB output? fmsb = (iii) Assume that the counter starts at zero. What will be the count after 635 input pulses? After 635 input pulse, Count =need help with parts D, E