Suppose a switch is built using a computer workstation and that it can forward packets at a rate of 500,000 packets per second, regardless (within limits) of size. Assume the workstation uses direct memory access (DMA) to move data in and out of its main memory, which has a bandwidth of 2 Gbps, and that the I/O bus has a bandwidth of 1 Gbps. At what packet size would the bus bandwidth become the limiting factor?

Suppose a switch is built using a computer workstation and that it can forward packets at a rate of 500,000 packets per second, regardless (within limits) of size. Assume the workstation uses direct memory access (DMA) to move data in and out of its main memory, which has a bandwidth of 2 Gbps, and that the I/O bus has a bandwidth of 1 Gbps. At what packet size would the bus bandwidth become the limiting factor?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

In a paged memory, the page hit ratio is 0.40. The time required to access a page in secondary memory is equal to 120 ns. The time required to access a page in primary memory is 15 ns. The average time required to access a page is
Assume a 1 Mbps shared connection (for example, an Ethernet bus). How long does it take to send a 1000-bit frame over this connection (in microseconds)?
Are there significant differences between asynchronous, synchronous, and isochronous connections?
q11- This question involves estimation of error handling overhead for a communication link which has a BER of 10−2 Forward error correct (FEC) Frame: Total 1144 bits 1024 bit of data 120 FEC bits Error Detection + automatic repeat request (ED + ARQ) Frame: Total 1074 bits 1024 bit of data 50 CRC bits a) Our task is to find the approximate frame error rate (FER) for FEC in percentage Answer: Answer b) Estimate the approximate overhead for ED + ARQ in percentage Answer: Answer
In what ways does the bus topology fall short, if at all?
I need the answer quickly
Q2: A gaming device has to transfer a high definition 1280 x 720 x 3 video frame @ 30 frames/sec. The 32-bit system bus operates in burst mode (burst size of 4). It takes one clock cycle to make one transfer through the bus and there is an overhead of five clock cycles per transfer. What should be the minimum bus frequency?
A computer has four page frames. The time of loading, time of last access, and the R and M bits for each page are as shown below (the times are in clock ticks) Page Loaded Last ref. R M 126 280 1 1 230 265 1 2 140 270 3 110 285 1 1 When page fault occurs, NRU removes page number
Consider a system with 36-bit addresses that employs both segmentation and paging. Assume each PTE and STE is 4-bytes in size Assume the largest possible segment table is 213 bytes and the largest possible page table is 216 bytes. How large is a page? How large in bytes is the largest possible segment? please explain and don't paste the quizlet picture
Computer Science If a system has a 4-MB address space, where each page is 4 KB, and page table accesses take 100 nS, how long does it take to load a complete page table? What fraction of a 100 mS time slice does this take?
I m going to post it second time please don't do it wrong. I will downvote.
What is principal of locality, for example if Level-1 can be accessed in 0.1 microseconds and Level-2 in 1 microsecond how we can access 1000 bytes in short time.