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Sequence Requirement The following are the sequence requirement for this project. • At first state (00) and third state (10): The system transitions to the next state when the long timer goes OFF. • At second state (01) and fourth state (11): The system transitions to the next state when the short timer goes OFF. Therefore, add the sequence requirement into state diagram from Lab 2, your new state diagram is shown in Figure 2.PART 1: DESIGN 1.1 Design a 2-bit binary counter using D flip-flops. Consider the long timer, TL and short timer, TS as your control inputs for the counter to work. As shown in Figure 1, the output from this counter, will be inputted to the combinational logic circuit. Show all your design steps (truth table, equation, and circuit implementation).

Sequence Requirement The following are the sequence requirement for this project. • At first state (00) and third state (10): The system transitions to the next state when the long timer goes OFF. • At second state (01) and fourth state (11): The system transitions to the next state when the short timer goes OFF. Therefore, add the sequence requirement into state diagram from Lab 2, your new state diagram is shown in Figure 2.PART 1: DESIGN 1.1 Design a 2-bit binary counter using D flip-flops. Consider the long timer, TL and short timer, TS as your control inputs for the counter to work. As shown in Figure 1, the output from this counter, will be inputted to the combinational logic circuit. Show all your design steps (truth table, equation, and circuit implementation).

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Sequence Requirement
The following are the sequence requirement for this project.
• At first state (00) and third state (10): The system transitions to the next state when the long timer goes OFF.
• At second state (01) and fourth state (11): The system transitions to the next state when the short timer goes OFF.
Therefore, add the sequence requirement into state diagram from Lab 2, your new state diagram is shown in Figure 2.PART 1: DESIGN
1.1 Design a 2-bit binary counter using D flip-flops. Consider the long timer, TL and short timer, TS as your control inputs for the counter to work. As shown in Figure 1, the output from this counter, will be inputted to the combinational logic circuit. Show all your design steps (truth table, equation, and circuit implementation).

TL=1 First state (S1): 00 Main: green (MG) Side: red (SR) Ts=0 TL=0 Fourth state (S4): Second state (S2): 11 01 Ts=1 Ts=1 Main: red (MR) Main: yellow (MY) Side: yellow (SY) Side: red (SR) TL=0 Ts=0 Third state (S3): 10 Main: red (MR) Side: green (SG) TL=1
Transcribed Image Text:TL=1 First state (S1): 00 Main: green (MG) Side: red (SR) Ts=0 TL=0 Fourth state (S4): Second state (S2): 11 01 Ts=1 Ts=1 Main: red (MR) Main: yellow (MY) Side: yellow (SY) Side: red (SR) TL=0 Ts=0 Third state (S3): 10 Main: red (MR) Side: green (SG) TL=1
TRAFFIC SIGNAL CONTROL LOGIC MR Red l. Main Yellow MY Binary number Green MG SR Red Sequential Logic Side Yellow SY SG Green Combinational Logic Traffic ight and interface unit Short Long 10 kHz Imer timer dock Long Trigger Short Trigger Timing Circuits
Transcribed Image Text:TRAFFIC SIGNAL CONTROL LOGIC MR Red l. Main Yellow MY Binary number Green MG SR Red Sequential Logic Side Yellow SY SG Green Combinational Logic Traffic ight and interface unit Short Long 10 kHz Imer timer dock Long Trigger Short Trigger Timing Circuits
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