Question 4) a. Calculate the maximum clock frequency that can be achieved by a processor with the following execution stage latencies with and without pipelining. Show your calculations to get full credit. Fetch: 2 ns, Decode: 4 ns, Execute: 4 ns, Write-back: 2 ns Max Clock Frequency without Pipelining: Max Clock Frequency with Pipelining:_ b. Assume the pipeline is initially empty and the processor is given 8 instructions to execute. However, the 4th instruction is an instruction whose operands depend on the result of the previous instruction. The remaining instructions are independent of each other. Given the instructions are not re-ordered, how long does it take to execute 8 such instructions with and without pipelining? What if the instructions can be reordered, how long does it take to execute those instructions with pipelining? Derive your solution by drawing the timing diagram of instructions passing through the pipeline stages.

Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
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Question 4)
a. Calculate the maximum clock frequency that can be achieved by a processor with the following
execution stage latencies with and without pipelining. Show your calculations to get full credit.
Fetch: 2 ns, Decode: 4 ns, Execute: 4 ns, Write-back: 2 ns
Max Clock Frequency without Pipelining:
Max Clock Frequency with Pipelining:_
b. Assume the pipeline is initially empty and the processor is given 8 instructions to execute. However, the
4th instruction is an instruction whose operands depend on the result of the previous instruction. The
remaining instructions are independent of each other. Given the instructions are not re-ordered, how long
does it take to execute 8 such instructions with and without pipelining? What if the instructions can be
reordered, how long does it take to execute those instructions with pipelining? Derive your solution by
drawing the timing diagram of instructions passing through the pipeline stages.
Total Time without Pipelining (instructions are not re-ordered):_
Total Time with Pipelining (instructions are not re-ordered):_
Total Time with Pipelining (instructions can be re-ordered):_
Transcribed Image Text:Question 4) a. Calculate the maximum clock frequency that can be achieved by a processor with the following execution stage latencies with and without pipelining. Show your calculations to get full credit. Fetch: 2 ns, Decode: 4 ns, Execute: 4 ns, Write-back: 2 ns Max Clock Frequency without Pipelining: Max Clock Frequency with Pipelining:_ b. Assume the pipeline is initially empty and the processor is given 8 instructions to execute. However, the 4th instruction is an instruction whose operands depend on the result of the previous instruction. The remaining instructions are independent of each other. Given the instructions are not re-ordered, how long does it take to execute 8 such instructions with and without pipelining? What if the instructions can be reordered, how long does it take to execute those instructions with pipelining? Derive your solution by drawing the timing diagram of instructions passing through the pipeline stages. Total Time without Pipelining (instructions are not re-ordered):_ Total Time with Pipelining (instructions are not re-ordered):_ Total Time with Pipelining (instructions can be re-ordered):_
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