QUESTION 4 a) States 4 types of shift register. b) Develop 4 bit serial in serial out (SISO) shift register using D Flip Flop. c) A synchronous counter count from number 1 to 6 as shown in Figure 5 is designed by using JK flip-flops. Assume all unused states are forced to don't care condition. 1 6 Figure 5 i) Construct the excitation table listing all the present state and the next state for the counter. ii) Determine the simplified equation for JA, KA, JB, KB, Jc and Kc by using К-map. iii) Draw the counter sequence using positive edge triggered JK flip-flop circuit with active high clock and other suitable logic gates.

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QUESTION 4
a)
States 4 types of shift register.
b)
Develop 4 bit serial in serial out (SISO) shift register using D Flip Flop.
c)
A synchronous counter count from number 1 to 6 as shown in Figure 5 is
designed by using JK flip-flops. Assume all unused states are forced to don't
care condition.
1
6.
Figure 5
i) Construct the excitation table listing all the present state and the next
state for the counter.
ii) Determine the simplified equation for JA, KA, JB, KB, Jc and Kc by using
К-map.
iii) Draw the counter sequence using positive edge triggered JK flip-flop
circuit with active high clock and other suitable logic gates.
Transcribed Image Text:QUESTION 4 a) States 4 types of shift register. b) Develop 4 bit serial in serial out (SISO) shift register using D Flip Flop. c) A synchronous counter count from number 1 to 6 as shown in Figure 5 is designed by using JK flip-flops. Assume all unused states are forced to don't care condition. 1 6. Figure 5 i) Construct the excitation table listing all the present state and the next state for the counter. ii) Determine the simplified equation for JA, KA, JB, KB, Jc and Kc by using К-map. iii) Draw the counter sequence using positive edge triggered JK flip-flop circuit with active high clock and other suitable logic gates.
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