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Question 1. Explain how accelerator inside the PL can access the DDR and OCM memory using AXI HP, AXI ACP and AXI GP ports. Explain the scenario (if any) in which accelerator access through AXI HP is faster than AXI ACP for осм. Explain the scenario (if any) in which accelerator access through AXI HP is faster than AXI ACP for DDR memory. High Performance AXI Controllers (AXI_HP) General Purpose AXI Slaves Cache General Coherent ACP Port Purpose AXI Masters PL Fabric PL Clocs MO MI MI M2 MD ASYNC Application Processing Unit Devc ASYNC ASYNC ASYNC ASYNC ASYNC Cortex-A9 DAP ASYNC ASYNC ASYNC NEON MMU LI VD Caches FIFO FIFO FIFO FIFO struction Dele Snop Slave Interconnect for Master Peripherals Snoop Control Unit AXI_HP to DDR Interconnect CPU eda CPU_ L2 Cache DMA Controller IOP IOP 512 KB Gos Masters Slave M1 CPU 2 Reg Data 6er OCM Interconnect IOP Oos CPU_1 Central Interconnect Readte On-chip ASYNC Requests jeg. mads RAM 250 B PASYNC ASYNC DDR Controller DOR a 3 Cok Synchronier M1 Master Interconnect Quality Cck Domains Service Prieity arespecied i Some ikka for Slave Peripherals CPU_2x

Question 1. Explain how accelerator inside the PL can access the DDR and OCM memory using AXI HP, AXI ACP and AXI GP ports. Explain the scenario (if any) in which accelerator access through AXI HP is faster than AXI ACP for осм. Explain the scenario (if any) in which accelerator access through AXI HP is faster than AXI ACP for DDR memory. High Performance AXI Controllers (AXI_HP) General Purpose AXI Slaves Cache General Coherent ACP Port Purpose AXI Masters PL Fabric PL Clocs MO MI MI M2 MD ASYNC Application Processing Unit Devc ASYNC ASYNC ASYNC ASYNC ASYNC Cortex-A9 DAP ASYNC ASYNC ASYNC NEON MMU LI VD Caches FIFO FIFO FIFO FIFO struction Dele Snop Slave Interconnect for Master Peripherals Snoop Control Unit AXI_HP to DDR Interconnect CPU eda CPU_ L2 Cache DMA Controller IOP IOP 512 KB Gos Masters Slave M1 CPU 2 Reg Data 6er OCM Interconnect IOP Oos CPU_1 Central Interconnect Readte On-chip ASYNC Requests jeg. mads RAM 250 B PASYNC ASYNC DDR Controller DOR a 3 Cok Synchronier M1 Master Interconnect Quality Cck Domains Service Prieity arespecied i Some ikka for Slave Peripherals CPU_2x

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question 1. Explain how accelerator inside the PL can access the DDR and OCM memory using AXI HP, AXI ACP and AXI GP ports. Explain the scenario (if any) in which accelerator access through AXI HP is faster than AX! ACP for OCM. Explain the scenario (if any) in which accelerator access through AXI HP is faster than AXI ACP for DDR memory. High Performance AXI Controllers (AXI_HP) General Cache General Purpose AXI Slaves Coherent Purpose AXI Masters PL Fabric ACP Port PL Clocks MO M M2 E M MD MI ASYNC Application Processing Unit Devc ASYNC ASYNC ASYNC ASYNC ASYNC Cortex-A9 DAP ASYNC ASYNC ASYNC < NEON MMU LI VD Caches nstruction FIFO FIFO FIFO FIFO Slave Interconnect for Master Peripherals Deta Snonp Snoop Control Unit AXI_HP to DDR CPU 2 CPU tade Interconnect L2 Cache DMA Controller CPU_2 IOP Masters IOP 512 KB Gos Oos MO M1 Slave Rea & M Data Ons 16 OCM Interconnect IOP Cos CPU_1 Central Interconnect RaadWte Requests (eg.8 mads 8 wites) On-chip ASYNC RAM OoS 256 KB ASYNC ÞASYNC 32- DDR Controller DDR 3x Clock Synchronieer - Master Interconnect Ma E MI MO Quality e Clodk Domains Service Priority X are specifed thin Some likacka for Slave Peripherals CPU 2
Transcribed Image Text:Question 1. Explain how accelerator inside the PL can access the DDR and OCM memory using AXI HP, AXI ACP and AXI GP ports. Explain the scenario (if any) in which accelerator access through AXI HP is faster than AX! ACP for OCM. Explain the scenario (if any) in which accelerator access through AXI HP is faster than AXI ACP for DDR memory. High Performance AXI Controllers (AXI_HP) General Cache General Purpose AXI Slaves Coherent Purpose AXI Masters PL Fabric ACP Port PL Clocks MO M M2 E M MD MI ASYNC Application Processing Unit Devc ASYNC ASYNC ASYNC ASYNC ASYNC Cortex-A9 DAP ASYNC ASYNC ASYNC < NEON MMU LI VD Caches nstruction FIFO FIFO FIFO FIFO Slave Interconnect for Master Peripherals Deta Snonp Snoop Control Unit AXI_HP to DDR CPU 2 CPU tade Interconnect L2 Cache DMA Controller CPU_2 IOP Masters IOP 512 KB Gos Oos MO M1 Slave Rea & M Data Ons 16 OCM Interconnect IOP Cos CPU_1 Central Interconnect RaadWte Requests (eg.8 mads 8 wites) On-chip ASYNC RAM OoS 256 KB ASYNC ÞASYNC 32- DDR Controller DDR 3x Clock Synchronieer - Master Interconnect Ma E MI MO Quality e Clodk Domains Service Priority X are specifed thin Some likacka for Slave Peripherals CPU 2
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