Question – 1: For the SR-Latches connected in the configuration below draw the output state F as a function of the time. Assume the clock rate is 1 kHz and "Data" input is as given below. Note that your answer must include only the time interval 0

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Question – 1: For the SR-Latches connected in the configuration below draw the output state F as a
function of the time. Assume the clock rate is 1 kHz and "Data" input is as given below. Note that your
answer must include only the time interval 0 <t< 12 ms.
Data
State= 1
t (ms)
t=0
t=2 t=3 t=4
t=8
t=12
Data
S
S
Clock
R
R
Question – 2: Assume that a user enters a series of numeric inputs where the numbers are in the range
from 0 to 9. Design a circuit to store the inputs using D-Latches. Assume all the numbers are recieved
as 4-bit binary inputs and "Enable" input is driven by a clock.
Transcribed Image Text:Question – 1: For the SR-Latches connected in the configuration below draw the output state F as a function of the time. Assume the clock rate is 1 kHz and "Data" input is as given below. Note that your answer must include only the time interval 0 <t< 12 ms. Data State= 1 t (ms) t=0 t=2 t=3 t=4 t=8 t=12 Data S S Clock R R Question – 2: Assume that a user enters a series of numeric inputs where the numbers are in the range from 0 to 9. Design a circuit to store the inputs using D-Latches. Assume all the numbers are recieved as 4-bit binary inputs and "Enable" input is driven by a clock.
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