Question 1: Assume a computer that has 32-bit integers. Show how each of the followingvalues would be stored sequentially in memory, starting at address 0x100, assuming eachaddress holds one byte. Be sure to extend each value to the appropriate number of bits. Youwill need to add more rows (addresses) to store all five values.a) OxAB123456b) 0x2BF876c) 0x8B0A1d) Ox1e) 0xFEDC1234Byte OrderAddressBig EndianLittle EndianOx1000x101Ox1020x1030x1040x1050x106Ox107

Memory Addressing: The memory addresses start from 0x100 and go sequentially. Each address…

Answered: Question 1: Assume a computer that has…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes (like LC-3): ADDRESS OxFFFF OXOCOE OXOCOD Ox0C0C OXOCOB OXOCOA 0x0C09 0x0000 CONTENTS 1111 1111 1111 1111 1111 1110 1101 1100 0001 1011 1100 0101 0110 0101 1000 0111 1100 0000 0100 0000 0011 0001 0101 0010 0000 1100 0000 1101 0000 0000 0000 0000 The table above shows the addresses in hex (base 16) and the contents at the corresponding address in binary (base 2). A.) What are the contents in hex of the memory location at following address in binary: 0000 1100 0000 1110? (Enter hex like the following example: Ox2A3F)
7
Make a quadruples address code out of the statement below: A = - A * (A + B ) - (B – C) / D
Suppose a computer using direct mapped cache has 232 words of main memory and a cache of 1024 blocks, where each cache block contains 32 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, block, and word fields? To which cache block will the memory reference 000063FA16 map?
Roll no 024
Suppose a computer using direct mapped cache has 236 bytes of byte-addressable main memory and a cache size of 1024 bytes, and each cache block contains 64 bytes. ⦁ How many blocks of main memory are there? ⦁ What is the format of a memory address as seen by cache, i.e., what are the sizes of the tag, block, and offset fields? ⦁ To which cache block will the memory address 0x13A4576B map?
4. The figure below shows an 8-way interleaved, byte-addressable memory. The total size of the memory is 4 KB. The elements A[i]G) of a 2-dimensional array A are 4-bytes (one-word) in length and can be stored in the memory as shown, where 0 < ij <7. The width of the bus between CPU and memory is 32 bits, that is, it can carry only one word at a time. Bank 1 Bank 7 Bank 0 31 7 A[7][0] A[I][0] A[0]|0] 32 A[7]1] 64 A[7]|2] A[I][2] A[0||2] RANKO 255 224 AI기기 A[I][7] A[0||7) RANKN ...... Since the address space of the memory is 4 KB, 12 bits are needed to uniquely identify each memory location, i.e., Addr[11:0]. Find out and explain which bits of the address will be used for: • Byte on bus: Addr […... :...] Bank index bits within a bank: Addr [.... .] • Chip select address bits within a rank: Addr […... .] • Rank bits: Addr […... :....]
Assume a computer has 32-bit integers. Show how the value OX0367ABC would be stored sequentially in memory, starting at address Ox100, on both a big endian machine and a little endian machine, assuming that each address holds one byte. Big Endian Address Ox100: type your answer. Big Endian Address Ox101: type your answer. Big Endian Address Ox102: type your answer. Big Endian Address Ox103: type your answer. .Little Endian Address Ox100: type your answer. Little Endian Address Ox101: type your answer. Little Endian Address Ox102: type your answer. Little Endian Address Ox103: type your answer..
Suppose we have a byte-addressable computer using fully associative mapping with 16-bit main memory addresses and 32 blocks of cache. Supposed also that each block contains 16 bytes. The size of the offset field is 19 bits and the size of the block field is 0.625 bytes.
Exercise: A computer has 4 frames. Page size is 2KB (2048). The loaded time, the R and M bits for each page are shown below Page Frame Loaded time M R 11 1 15 3 13 4 5 5 7 6. 3 3 Question: compute the physical address of the following virtual address a) 1000 using FIFO b) 3100 using NRU c) 3100 using LRU d) 6200 using Second chance Note: consider each case separately
6. Write down the three-address codes for the following code segment. S := 0, I := 0 WHILE I < 10 DO S := s + X[I] I := I + 1 ENDWHILE
5. suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) how many blocks of main memory are there? b) what is the format of a memory address as seen by the cache ; that is, what are the size of the tag and offset field. c) To which cache block will the memory address 0x01D872 map?

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